• 전자공학회논문지A
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• 제31A권7호
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• pp.76-84
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• 1994

The characteristics of 3 inch wafer scale GaAs epitaxial wafer grown by molecular beam epitaxy for LSI process application were studied. The thickness and doping uniformity are characterized and discussed. The growth temperature and growth rate were $600^{\circ}C$ by pyrometer, and 1 $\mu$m/h, respectively. It was found that thickness and doping uniformity were 3.97% and 4.74% respectively across the full 3 inch diameter GaAs epitaxial layer. Also, ungated MESFETs have been fabricated and saturation current measurement showed 4.5% uniformity on 3 inch, epitaxial layer, but uniformity of threshold voltage increase up to 9.2% after recess process for MESFET device.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 추계학술대회
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• pp.1448-1452
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• 2003

A scratch tester was developed to evaluate the adhesive strength at interface between thin-film and substrate(silicon wafer). Under force control, the scratch tester can measure the normal and the tangential forces simultaneously as the probe tip of the equipment approaches to the interface between thin-film and substrate of wafer. The capacity of each component of force sensor is 0.1 N ${\sim}$ 100 N. In addition, the tester can detect the signal of elastic wave from AE sensor(frequency range of 900 kHz) attached to the probe tip and evaluate the bonding strength of interface. Using the developed scratch tester, the feasibility test was performed to evaluate the adhesive strength of thin-film.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.7-8
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• 2005

The pseudo MOSFET measurement technique has been a simple and rapid method for characterization of SOI wafers without any device fabrication process. We adopted the pseudo MOSFET technique to examine the surface silicon film thickness dependence of electrical properties of SOI wafer. The measurements showed that turn-on voltage increased and electron mobility decreased as the SOI film thickness was reduced in the SOI film thickness of less than 20 nm region.

• 반도체디스플레이기술학회지
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• 제1권1호
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• pp.15-19
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• 2002

A new vacuum packaging process in wafer level is developed for the surface micromachining devices using glass silicon anodic bonding technology. The inside pressure of the packaged device was measured indirectly by the quality factor of the mechanical resonator. The measured Q factor was about 5$\times10^4$ and the estimated inner pressure was about 1 mTorr. And it is also possible to change the inside pressure of the packaged devices from 2 Torr to 1 mTorr by varying the amount of the Ti gettering material. The long-term stability test is still on the way, but in initial characterization, the yield is about 80% and the vacuum degradation with time was not observed.

• 반도체디스플레이기술학회지
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• 제9권4호
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• pp.39-43
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• 2010

According to recent changes in industry for the semiconductor device, a gap between patterns in wafer is getting narrow. And this narrow gap makes a failure of uniform deposition between center and edge on the wafer. In this paper, for solving this problem, we analyze and manipulate the gas flow inside of the HDP CVD chamber by using CFD(Computational Fluid Dynamics). This simulation includes design manipulations in heights of the chamber and shape of center nozzle in the upper side of the chamber. The result of simulation shows 1.28 uniformity which is lower 3% than original uniformity.

• ETRI Journal
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• 제36권4호
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• pp.617-624
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• 2014

Through-silicon via (TSV) technology provides much of the benefits seen in advanced packaging, such as three-dimensional integrated circuits and 3D packaging, with shorter interconnection paths for homo- and heterogeneous device integration. In TSV, a destructive cross-sectional analysis of an image from a scanning electron microscope is the most frequently used method for quality control purposes. We propose a quantitative evaluation method for TSV etch profiles whereby we consider sidewall angle, curvature profile, undercut, and scallop. A weighted sum of the four evaluated parameters, nominally total score (TS), is suggested for the numerical evaluation of an individual TSV profile. Uniformity, defined by the ratio of the standard deviation and average of the parameters that comprise TS, is suggested for the evaluation of wafer-to-wafer variation in volume manufacturing.

• ETRI Journal
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• 제35권4호
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• pp.603-609
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• 2013

In this paper, we present a 600-V reverse conducting insulated gate bipolar transistor (RC-IGBT) for soft and hard switching applications, such as general purpose inverters. The newly developed RC-IGBT uses the deep reactive-ion etching trench technology without the thin wafer process technology. Therefore, a freewheeling diode (FWD) is monolithically integrated in an IGBT chip. The proposed RC-IGBT operates as an IGBT in forward conducting mode and as an FWD in reverse conducting mode. Also, to avoid the destructive failure of the gate oxide under the surge current and abnormal conditions, a protective Zener diode is successfully integrated in the gate electrode without compromising the operation performance of the IGBT.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권6호
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• pp.271-277
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• 2002

In this paper, a MEMS silicon package is newly designed, fabricated for HMIC, and characterized for microwave and millimeter-wave device applications. The proposed package is fabricated by using two high resistivity silicon substrates and surface/bulk micromachining technology. It has a good performance characteristic such as -20㏈ of $S_11$/ and -0.3㏈ of $S_21$ up to 20㎓, which is useful in microwave region. It has also better heat transfer characteristics than the commonly used ceramic package. Since the proposed silicon MEMS package is easy to fabricate and wafer level chip scale packaging is also possible, the production cost can be much lower than the ceramic package. Since it will be a promising low-cost package for mobile/wireless applications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.11-12
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• 2007

The electrical characteristics of strained-SOI wafer were evaluated by using pseudo-MOSFET. The electrical characteristics of sSOI pseudo-MOSFET were superior to conventional SOI device. Moreover, the electrical characteristics were enhanced by forming gas anneal due to reduction of back interface trap density between substrate and buried oxide.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.75-78
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• 2000

This paper is estimated to enhance yield improvement and device reliability using PDM(plasma damage monitoring) system capable of in-suit detection about plasma nonuniformity. PDM Tool is the non-contact method of wafer and surface potential electrode(kelvin probe). Its tool measures Vox(oxide barrier) with charge created by plasma. It's possible to inspect the wafer damage generated by plasma charge and analysis of in-situ monitoring data. we obtained the good data which is continuously prevented from plasma damage using its tool for 10weeks. This tool is contributed to preventive steps contemporaneously inspecting the difference of inter-chamber.