[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.4218/etrij.14.0113.0828

Quantitative Evaluation Method for Etch Sidewall Profile of Through-Silicon Vias (TSVs)

Son, Seung-Nam (Department of Electronic Engineering, Myongji University, Department of Package Development, Amkor Korea)
Hong, Sang Jeen (Department of Electronic Engineering, Myongji University)

Publication Information

ETRI Journal / v.36, no.4, 2014 , pp. 617-624 More about this Journal

Abstract

Through-silicon via (TSV) technology provides much of the benefits seen in advanced packaging, such as three-dimensional integrated circuits and 3D packaging, with shorter interconnection paths for homo- and heterogeneous device integration. In TSV, a destructive cross-sectional analysis of an image from a scanning electron microscope is the most frequently used method for quality control purposes. We propose a quantitative evaluation method for TSV etch profiles whereby we consider sidewall angle, curvature profile, undercut, and scallop. A weighted sum of the four evaluated parameters, nominally total score (TS), is suggested for the numerical evaluation of an individual TSV profile. Uniformity, defined by the ratio of the standard deviation and average of the parameters that comprise TS, is suggested for the evaluation of wafer-to-wafer variation in volume manufacturing.

Keywords

Through-silicon via; etch-profile evaluation; quality control;

Citations & Related Records

Reference

1	S.W. Yoon et al., "3D TSV Processes and its Assembly/Packaging Technology," IEEE Int. Conf. Syst. Integr., San Francisco, CA, USA, Sept. 28-30, 2009, pp. 1-5.
2	E. Nowak et al., "Intrinsic Fluctuations in Vertical NAND Flash Memories," Symp. VLSI Technol., Honolulu, HI, USA, June 12-14, 2012, pp. 21-22.
3	V.S. Rao et al., "TSV Interposer Fabrication for 3D IC Packaging," Electron. Packag. Technol. Conf., Singapore, Dec. 9-11, 2009, pp. 431-437.
4	E. Bär, J. Lorenz, and H. Ryssel, "Simulation of the Influence of Via Sidewall Tapering on Step Coverage of Sputter-Deposited Barrier Layers," Microelectron. Eng., vol. 64, no. 1-4, Oct. 2002, pp. 321-328. DOI
5	W.H. Teh et al., "Magnetically-Enhanced Capacitively-Coupled Plasma Etching for 300 mm Wafer-Scale Fabrication of Cu Through-Silicon-Vias for 3D Logic Integration," IEEE Int. Interconnect Technol. Conf., Sapporo, Japan, June 1-3, 2009, pp. 53-55.
6	K.P. Han et al., "Matrix Scoring Method for the Evaluation of TSV Development Using a Magnetically Enhanced Plasma Etcher," ECS Meeting, Las Vegas, NV, USA, Oct. 2010.
7	V.N. Sekhar et al., "Non-destructive Testing of a High Dense Small Dimension Through Silicon Via (TSV) Array Structures by Using 3D X-ray Computed Tomography Method (CT scan)," Electron. Packag. Technol. Conf., Singapore, Dec. 8-10, 2010, pp. 462-466.
8	Z. Xu and J.-Q. Lu, "High-Speed Design and Broadband Modeling of Through-Strata-Via (TSVs) in 3D Integration," IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 2, Feb. 2011, pp. 154-162. DOI
9	J.V. Olmen et al., "3D Stacked IC Demonstrator Using Hybrid Collective Die-to-Wafer Boding with Copper Through Silicon Vias (TSV)," IEEE Int. Conf. 3D Syst. Integr., San Francisco, CA, USA, Sept. 28-30, 2009, pp. 1-5.