• 대한기계학회논문집B
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• 제34권2호
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• pp.105-111
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• 2010

양극산화법과 DRIE 법으로 제작된 다공성 실리콘막을 이용하여 두 종류의 전기침투 펌프를 제작하였다. 펌프의 성능은 유기용매를 이용하여 유량과 단위전류당 유량으로 측정하였다. 두 종류 펌프 모두 기존의 다공성 유리막으로 제작된 전기침투 펌프보다 성능이 우월했다. 특히 DRIE 법으로 제작된 다공성 실리콘막은 유량과 단위전류당 유량이 모두 월등한 성능을 보였다. DRIE 법은 널리 알려진 방법이기에 이와 같이 제작된 펌프는 다양한 응용 분야에 비교적 쉽게 적용될 것으로 기대된다.

• 전기학회논문지
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• 제60권2호
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• pp.362-369
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• 2011

In this paper, optimal deep reactive ion etching (DRIE) process conditions for fused quartz were experimentally determined by Taguchi method, and fused quartz-based micro cantilevers were fabricated. In addition, comparative study on Q-factors of fused quartz and silicon micro cantilevers was performed. Using a silicon layer as an etch mask for fused quartz DRIE process, different 9 flow rate conditions of $C_4F_8$, $O_2$ and He gases were tested and the optimum combination of these factors was estimated. Micro cantilevers based on fused quartz were fabricated from this optimal DRIE condition. Through conventional silicon DRIE process, single-crystalline silicon micro cantilevers whose dimensions were similar to those of quartz cantilevers were also fabricated. Mechanical Q-factors were calculated to compare intrinsic damping properties of those two materials. Resonant frequencies and Q-factors were measured for the cantilevers having fixed widths and thicknesses and different lengths. The Q-factors were in a range of 64,000 - 108,000 for fused quartz cantilevers and 31,000 - 35,000 for silicon cantilevers. The experimental results supported that fused quartz had a good intrinsic damping property compared to that of single crystalline silicon.

• 한국전기전자재료학회논문지
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• 제15권11호
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• pp.958-962
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• 2002

This paper reports on the fabrication of free-standing microstructures by DRIE (deep reactive ion etching). SOI (Si-on-insulator) structures with buried cavities are fabricated by SDB (Si-wafer direct bonding) technology and electrochemical etch-stop. The cavity was formed the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the formed cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing (100$0^{\circ}C$, 60 min.), the SDB SOI structure with a accurate thickness and a good roughness was thinned by electrochemical etch-stop in TMAH solution. Finally, it was fabricated free-standing microstructures by DRIE. This result indicates that the fabrication technology of free-standing microstructures by combination SDB, electrochemical etch-stop and DRIE provides a powerful and versatile alternative process for high-performance bulk micromachining in MEMS fields.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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• pp.129-130
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• 2008

In this paper, optimal DRIE process conditions for fused quartz are experimentally determined by Taguchi method to develop high-performance inertial sensors based on the fused quartz material, which is known to have high Q-factors. Using Si layer as an etch mask, which was formed by previously developed bonding process of the fused quartz and Si wafer, fused quartz DRIE process was performed. Different 9 flow rate conditions of $C_4F_8$, $O_2$, He gas have been tested and the optimum combination of these factors was estimated. By this work, the ability to fabricate high aspect ratio fused quartz structure was confirmed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.741-744
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• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.739-742
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• 2002

This paper described on the fabrication of microstructures by DRIE(deep reactive ion etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing($1000^{\circ}C$, 60 min.), The SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as an accurate thickness control and a good flatness.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2009년도 춘계학술대회 논문집
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• pp.239-241
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• 2009

DRIE(Deep Ion Reactive Etching) 공정은 실리콘 웨이퍼를 식각하는 기술로서 Si wafer 비아 홀 제조에 주로 사용되고 있다. 즉, DRIE 공정은 식각 및 보호층 증착을 반복함으로써 직진성 식각을 가능하게 하는 공정이다. 또한, 3차원 적층 실장에서 Si wafer 비아 홀에 결함없이 효과적으로 구리 충진을 하기 위해서는 직각형 via보다 경사벽을 가진 via가 형상적으로 유리하다. 본 연구에서는 3차원 적층을 위한 Si wafer 비아 홀의 결함 없는 효과적인 구리 충진을 위해, DRIE 공정을 이용하여 기존의 경사벽을 가지는 via 흘 형성 공정보다 더욱 효과적인 공정을 개발하였다.

• 한국정밀공학회지
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• 제26권12호
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• pp.32-40
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• 2009

• 한국레이저가공학회지
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• 제13권4호
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• pp.7-13
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• 2010

Today, the most common process for generating Through Silicon Vias (TSVs) for 3D ICs is Deep Reactive Ion Etching (DRIE), which allows for high aspect ratio blind holes with low surface roughness. However, the DRIE process requires a vacuum environment and the use of expensive masks. The advantage of using lasers for TSV drilling is the higher flexibility they allow during manufacturing, because neither vacuum nor lithography or masks arc required and because lasers can be applied even to metal and to dielectric layers other than silicon. However, conventional nanosecond lasers have the disadvantage of causing heat affection around the target area. By contrast, the use of a picosecond laser enables the precise generation of TSVs with less heat affected zone. In this study, we conducted a comparison of thermalization effects around laser-drilled holes when using a picosecond laser set for a high pulse energy range and a low pulse energy range. Notably, the low pulse energy picosecond laser process reduced the experimentally recast layer, surface debris and melts around the hole better than the high pulse energy process.

• 대한금속재료학회지
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• 제48권11호
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• pp.1028-1034
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• 2010

In the development of 3D package, through silicon via (TSV) formation technology by using deep reactive ion etching (DRIE) is one of the key processes. We performed the Bosch process, which consists of sequentially alternating the etch and passivation steps using $SF_6$ with $O_2$ and $C_4F_8$ plasma, respectively. We investigated the effect of changing variables on vias: the gas flow time, the ratio of $O_2$ gas, source and bias power, and process time. Each parameter plays a critical role in obtaining a specified via profile. Analysis of via profiles shows that the gas flow time is the most critical process parameter. A high source power accelerated more etchant species fluorine ions toward the silicon wafer and improved their directionality. With $O_2$ gas addition, there is an optimized condition to form the desired vertical interconnection. Overall, the etching rate decreased when the process time was longer.