• Transactions on Control, Automation and Systems Engineering
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• v.2 no.3
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• pp.163-168
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• 2000

The problems of mixed $H_2/H_{\infty}$ filtering design fer continuous and discrete time linear systems with time delay are investigated. The main purpose is to design a stable mixed $H_2/H_{\infty}$ filter which minimizes the H$_2$Performance measure satisfying a prescribed H$_{\infty}$ norm bound on the closed loop system in continuous-time case and discrete-time case, respectively. The sufficient conditions of existence of filter, the mixed $H_2/H_{\infty}$ filter design method, and the upper bound of performance measure are proposed by LMI(linear matrix inequality) techniques in terms of all finding variables. Also, we present optimization problems in order to get the optimal mixed $H_2/H_{\infty}$ filter in continuous and discrete time case, respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.89-94
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• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10a
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• pp.157-160
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• 1996

Physical systems axe generally continuous-time in nature. However as the data measured from these systems is generally in the form of discrete samples, and most modern signal processing is performed in the discrete-time domain, discrete-time models are employed. This paper describes methods for estimating the coefficients of continuous-time system within a closed loop control system. The method employs a recursive estimation algorithm to identify the coefficients of a discrete-time bilinear-operator model. The coefficients of the discrete-time bilinear-operator model closely approximate those of the corresponding continuous-time Laplace transform transfer function.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.65-73
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• 2007

This paper presents a low power CMOS continuous-time $\Sigma\Delta$ (sigma-delta) modulator for UMTS receivers. The loop filter of the continuous-time $\Sigma\Delta$ modulator consists of an active-RC filter which performs high linearity characteristics and has a simple tuning circuit for low power operating system The architecture of this modulator is the $3^{rd}-order$ 4-bit single loop configuration with a 24 of OSR (Oversampling Ratio) to increase the power efficiency. The modulator includes a half delay feedback path to compensate the excess loop delay. The experimental results of the modulator are 71dB, 65dB and 74dB of the peak SNR, peak SMR and dynamic range, respectively. The continuous-time $\Sigma\Delta$ modulator is fabricated in a 0.18-um 1P4M CMOS standard process and dissipates 15mW for a single supply voltage of 1.8V.

• Journal of IKEEE
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• v.23 no.2
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• pp.461-468
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• 2019

A continuous-time Delta-Sigma ADC has various benefits; it does not require an explicit anti-aliasing filter, and it is able to handle wider-band signals with less power consumption in comparison with a discrete-time Delta-Sigma ADC. However, it inherently needs to sample the signal with a high-speed clock, necessitating a complex decimation filter that operates at high speed in order to convert the modulator output to a low-rate high-resolution digital signals without causing aliasing. This paper proposes a continuous-time Delta-Sigma ADC architecture that employs pulse-width modulation and shows that the proposed architecture lends itself to a simpler implementation of the decimation filter using a lookup table.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.319-329
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• 2016

High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuit-level simulation using Verilog-A blocks are used to validate our approach.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.06a
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• pp.1005-1010
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• 2005

In this paper, it is presented a frequency modulated continuous wave radar (FMCW) for distance measurement. The frequency range is $10{\sim}11$ GHz and the sweep time of the signal is 100 ms. The test target is 0.8 m2 of metal plate. The experiment is performed in open ground and the pyramidal horn antenna of about 22 dBi gain is used. The beat frequency according to the target moving to 40 m is measured. There is a good agreement between measured and calculated results. But the resolution of the FMCW radar is not good such as about 10 cm. It is result from the nonlinear signal of voltage controlled oscillator (VCO). To improve the nonlinear characteristic of VCO, a high pass filter and phase locked loop (PLL) frequency synthesizer are included in the radar system.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.323-325
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• 1993

In this paper, an output feedback controller is proposed for continuous time-invariant linear systems. The proposed controller, LQ-FIR consists of an LQ control gain and an optimal FIR filter. The LQ-FIR controller is derived, and the stability of the closed loop system is proved. The bounds of parameter variations guaranteeing the closed loop stability are obtained, when the LQ-FIR controller is applied to the system with model uncertainties.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.51-59
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• 2009

This paper presents the design of continuous-time sigma-delta modulator for acoustic sensor. The feedforward structure without summing block is used to reduce power consumption of sigma-delta modulator. A high-linearity active-RC filter is used to improve resolution of sigma-delta modulator. Excess loop delay problem in conventional continuous-time sigma-delta modulators is solved by our proposed architecture. A low power, high resolution fourth-order continuous-time sigma-delta modulator with 1-bit quantization was realized in a 0.13-${\mu}m$ 1-Poly 8-metal CMOS technology, with a core area of $0.58\;mm^2$. Simulation results show that the modulator achieves 91.3-dB SNR over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating $290{\mu}W$ from a 3.3-V supply.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.8
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• pp.883-888
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• 1999

To obtain high positioning auccuracy for a long, flex bleman Ipulator, residual vibration must be removed from the tip motion. But it is difficult to control the vibration of low frequency. There are open-loop and closed loop methods in the elimination of the residual vibration. We inroduce input shaping technique has been used as a simple open-loop method of controlling the residual vibration of a flexible manipulator. Design of input shaper in the continuous time domain is complicated. This paper presents a new technique that designs input shaper in the z-domain and analyzes input shaping method in the z-domain. This technique is simple and easy to design input shaper.