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A Low-Power CMOS Continuous-Time Sigma-Delta Modulator for UMTS Receivers  

Lim, Jin-Up (University of Seoul, Department of Electrical and Computer Engineering)
Choi, Joong-Ho (University of Seoul, Department of Electrical and Computer Engineering)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.8, 2007 , pp. 65-73 More about this Journal
Abstract
This paper presents a low power CMOS continuous-time $\Sigma\Delta$ (sigma-delta) modulator for UMTS receivers. The loop filter of the continuous-time $\Sigma\Delta$ modulator consists of an active-RC filter which performs high linearity characteristics and has a simple tuning circuit for low power operating system The architecture of this modulator is the $3^{rd}-order$ 4-bit single loop configuration with a 24 of OSR (Oversampling Ratio) to increase the power efficiency. The modulator includes a half delay feedback path to compensate the excess loop delay. The experimental results of the modulator are 71dB, 65dB and 74dB of the peak SNR, peak SMR and dynamic range, respectively. The continuous-time $\Sigma\Delta$ modulator is fabricated in a 0.18-um 1P4M CMOS standard process and dissipates 15mW for a single supply voltage of 1.8V.
Keywords
Continuous-time; Sigma-delta modulator; UMTS; Single-loop; CMOS;
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