대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

어쿠스틱 센서 IC용 4차 단일 비트 연속 시간 시그마-델타 모듈레이터

A $4^{th}$-Order 1-bit Continuous-Time Sigma-Delta Modulator for Acoustic Sensor

  • 김형중 (한양대학교 전자컴퓨터공학) ;
  • 이민우 (한양대학교 전자컴퓨터공학) ;
  • 노정진 (한양대학교 전자컴퓨터공학)
  • Kim, Hyoung-Joong (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.) ;
  • Lee, Min-Woo (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.) ;
  • Roh, Jeong-Jin (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.)
  • 발행 : 2009.03.25
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초록

본 논문에서는 어쿠스틱 센서 IC 용 연속 시간 시그마-델타 모듈레이터를 구현하였다. 모듈레이터의 전력 소모를 최소화하기 위해 summing 단의 필요성을 제거한 피드-포워드 (feed-forward) 구조로 설계 하였으며, 해상도를 높이기 위해 선형성이 우수한 active-RC 필터를 사용하여 설계 하였다. 또한 초과 루프 지연 시간 (excess loop delay)에 의한 성능 저하를 방지하기 위한 회로 기법을 제안 하였다. 저 전압, 고 해상도의 4차 단일 비트 연속 시간 시그마-델타 모듈레이터는 $0.13{\mu}m$ 1 poly 8 metal CMOS 표준 공정으로 제작하였으며 코어 크기는 $0.58\;mm^2$ 이다 시뮬레이션 결과 25 kHz 의 신호 대역 내에서 91.3 dB의 SNR(signal to noise ratio)을 얻었고 전체 전력 소모는 $290{\mu}W$ 임을 확인하였다.

This paper presents the design of continuous-time sigma-delta modulator for acoustic sensor. The feedforward structure without summing block is used to reduce power consumption of sigma-delta modulator. A high-linearity active-RC filter is used to improve resolution of sigma-delta modulator. Excess loop delay problem in conventional continuous-time sigma-delta modulators is solved by our proposed architecture. A low power, high resolution fourth-order continuous-time sigma-delta modulator with 1-bit quantization was realized in a 0.13-${\mu}m$ 1-Poly 8-metal CMOS technology, with a core area of $0.58\;mm^2$. Simulation results show that the modulator achieves 91.3-dB SNR over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating $290{\mu}W$ from a 3.3-V supply.

키워드

참고문헌

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