• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.59-64
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• 2013

In this paper, a capacitor multiplier with good frequency characteristics has been proposed. Effective capacitance of conventional capacitor multiplier decreases as frequency increases due to internal series resistance. On the other hand, the proposed capacitor multiplier using cascode structure has smaller internal resistance, thus shows good frequency characteristics. Conventional and proposed capacitor multiplier were fabricated using Samsung $0.13{\mu}m$ CMOS process and frequency characteristics of capacitor multipliers were measured using LPF. Measurement results show that the conventional capacitor multiplier has maximum 53% of capacitance error, however the proposed multiplier has less than 10% of capacitance error for the frequency change from 100kHz to 1MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7A
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• pp.568-573
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• 2009

This paper presents a step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in O.13um CMOS standard process. In an effort to decrease system volume, this paper proposes the on chip compensation circuit using capacitor multiplier method. Capacitor multiplier method can minimize error amplifier's compensation capacitor size by 10%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87.2% for the output voltage of 1.2V (input voltage : 3.3V), maximum load current 500mA, and 25mA output ripple current. This voltage mode controled buck converter has 1MHz switching frequency.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.739-742
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• 2002

This article proposes a Four-Quadrant Analog Multiplier (4-QAM) applying switched-capacitor and pulse-width amplitude modulation (PWAM) principles. The features of the presented circuit are that it can function as analog multiplier with a wide dynamic range of input signal and no disturbing from deviation of carrier frequency of PWM signal. In addition, the circuit detail is simpler than that of the previously proposed circuits. It is then easy and applicable for employing it into Integrated Circuit (IC) realization to especially operate in low-frequency and low-power applications. The experimental results granted are in correspondence to the theoretical analysis.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.56-62
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• 2013

We present a rectifier for wireless power transmission using multiplier configuration in layout for MOSFETs which works at 13.56 MHz, designed to fit in CMOS process where conventionally used diodes are replaced with the cross-coupled MOSFETs. Full bridge rectifier structure without comparators is employed to reduce current consumption and to be working up to higher frequency. Multiplier configuration designed in layout reduces time delay originated from parasitic series resistance and shunt capacitance at each finger due to long connecting layout, leading to fast transition from on-state to off-state cross-coupled circuit structure and vice versa. The power conversion efficiency is significantly increased due to this fast transition time. The rectifier is fabricated in $0.11{\mu}m$ CMOS process, RF to DC power conversion efficiency is measured as 86.4% at the peak, and this good efficiency is maintained up to 600 MHz, which is, to our best knowledge, the highest frequency based on cross-coupled configuration.

• ETRI Journal
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• v.30 no.6
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• pp.826-832
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• 2008

The metal-ferroelectric-metal (MFM) capacitor in the ferroelectric random access memory (FeRAM) embedded RFID chip is used in both the memory cell region and the peripheral analog and digital circuit area for capacitance parameter control. The capacitance value of the MFM capacitor is about 30 times larger than that of conventional capacitors, such as the poly-insulator-poly (PIP) capacitor and the metal-insulator-metal (MIM) capacitor. An MFM capacitor directly stacked over the analog and memory circuit region can share the layout area with the circuit region; thus, the chip size can be reduced by about 60%. The energy transformation efficiency using the MFM scheme is higher than that of the PIP scheme in RFID chips. The radio frequency operational signal properties using circuits with MFM capacitors are almost the same as or better than with PIP, MIM, and MOS capacitors. For the default value specification requirement, the default set cell is designed with an additional dummy cell.

• Journal of Power Electronics
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• v.18 no.3
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• pp.662-671
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• 2018

This paper presents a new structure for a step up dc-dc converter, which has several advantageous features. Firstly, the input dc source and the clamped capacitor are connected in series to transfer energy to the load through dual voltage multiplier cells. Therefore, the proposed converter can produce a very high voltage and a high conversion efficiency. Secondly, a double voltage clamped circuit is introduced to the primary side of the coupled inductor. The energy of the leakage inductance of the coupled inductor is recycled and the inrush current problem of the clamped circuits can be shared equally by two synchronous clamped capacitors. Therefore, the voltage spike of the switch tube is solved and the current stress of the diode is reduced. Thirdly, dual voltage multiplier cells can absorb the leakage inductance energy of the secondary side of the coupled inductor to obtain a higher efficiency. Fourthly, the active switch turns on at almost zero current and the reverse-recovery problem of the diodes is alleviated due to the leakage inductance, which further improves the conversion efficiency. The operating principles and a steady-state analysis of the continuous, discontinuous and boundary conduction modes are discussed in detail. Finally, the validity of this topology is confirmed by experimental results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.1-7
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• 2008

This paper proposes 3.3V input and 1.8V output voltage mode step-down DC-DC buck converter for wireless mobile system which is designed in a standard 0.35$\mu$m CMOS process. The proposed capacitor multiplier method can minimize error amplifier compensation block size by 30%. It allows the compensation block of DC-DC converter be easily integrated on a chip. Also, we improve efficiency to 3% using low power buffer. Measurement result shows that the circuit has less than 1.17% output ripple voltage and maximum 83.9% power efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.7
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• pp.513-518
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• 2016

The piezoelectric actuating device is known for its large power density and simple structure. It can generate a larger force than a conventional actuator and has also wide bandwidth with fast response in a compact size. To control the piezoelectric actuator, we need an analog signal conditioning circuit as well as digital microcontrollers. Conventional microcontrollers are not equipped with an analog part and need digital-to-analog converters, which makes the system bulky compared with the small size of piezoelectric devices. To overcome these weaknesses, we are developing a single-chip controller that can handle analog and digital signals simultaneously using mixed-signal FPGA technology. This gives more flexibility than traditional fixed-function microcontrollers, and the control speed can be increased greatly due to the parallel processing characteristics of the FPGA. In this paper, we developed a floating-point multiplier, PWM generator, 80-kHz power control loop, and 1-kHz position feedback control loop using a single mixed-signal FPGA. It takes only 50 ns for single floating-point multiplication. The PWM generator gives two outputs to control the charging and discharging of the high-voltage output capacitor. Through experimentation and simulation, it is demonstrated that the designed control loops work properly in a real environment.