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http://dx.doi.org/10.6109/jkiice.2021.25.11.1627

Low Power ADC Design for Mixed Signal Convolutional Neural Network Accelerator  

Lee, Jung Yeon (Mixed Signal Integrated System Lab, ChungBuk National University)
Asghar, Malik Summair (Mixed Signal Integrated System Lab, ChungBuk National University)
Arslan, Saad (Department of Electrical and Computer Engineering, COMSATS University Islamabad)
Kim, HyungWon (Mixed Signal Integrated System Lab, ChungBuk National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.25, no.11, 2021 , pp. 1627-1634 More about this Journal
Abstract
This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛2, power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.
Keywords
Convolution neural networks; Split-capacitor-based DAC; Approximation analog-to-digital converter; Artificial intelligence; System on chip design;
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1 S. Lan, C. Yuan, Y. Y. H. Lam, and L. Siek, "An ultra low-power rail-to-rail comparator for ADC designs," 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, 2011.
2 X. He, J. He, M. Cai, and Z. Jing, "A low power switching method with variable comparator reference voltage and split capacitor array for SAR ADC," in Proceedings of the IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong kong, pp. 379-382, 2016
3 S. H. Wang and C. C. Hung, "A 0.3V 10b 3MS/s SAR ADC With Comparator Calibration and Kickback Noise Reduction for Biomedical Applications," in IEEE Transactions on Biomedical Circuits and Systems, vol. 14, no. 3, pp. 558-569, Jun. 2020.   DOI
4 B. P. Ginsburg and A. P. Chandrakasan, "An energy-efficient charge recycling approach for a SAR converter with capacitive DAC," 2005 IEEE International Symposium on Circuits and Systems, Kobe, vol. 1, pp. 184-187, 2005.
5 H. J. Kang and H. W. Kim. "A Highly Energy-Efficient Architecture of SAR ADC Based on Successive Scaling of Reference Voltages," The Sixth International Conference On Consumer Electronics (ICCE) Asia, pp. 143-147, 2016
6 V. Hariprasath, J. Guerber, S. H. Lee, and U. K. Moon, "Merged capacitor switching based SAR ADC with highest switching energy-efficiency," in Electronics Letters, vol. 46, no. 9, pp. 620-621, Apr. 2010.   DOI
7 L. Sun, B. Li, A. K. Y. Wong, W. T. Ng, and K. P. Pun, "A Charge Recycling SAR ADC With a LSB-Down Switching Scheme," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 2, pp. 356-365, Feb. 2015   DOI
8 S. Sekine, T. Matsuura, R. Kishida, and A. Hyogo, "A Novel C-2 αC Ladder Based Non-binary DAC for SAR-ADC Using Unit Capacitors," 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 457-462, 2018.