Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2008.06a
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- Pages.537-538
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- 2008
Design of a Step-Down DC-DC converter with On-chip Capacitor multiplyed Compensation circuit
온칩된 커패시터 채배기법 적용 보상회로를 갖는 DC to DC 벅 변환기 설계
- Park, Seung-Chan (Dept. of Electronic Engineering INHA University) ;
- Lim, Dong-Kyun (Dept. of Electronic Engineering INHA University) ;
- Yoon, Kwang-Sub (Dept. of Electronic Engineering INHA University)
- Published : 2008.06.18
Abstract
A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is
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