• Title/Summary/Keyword: CPS (Counter Pocket Source)

Search Result 9, Processing Time 0.024 seconds

Simulation-based ESD protection performance of modified DDD_NSCR device with counter pocket source structure for high voltage operating I/O application (고전압 동작용 I/O 응용을 위해 Counter Pocket Source 구조를 갖도록 변형된 DDD_NSCR 소자의 ESD 보호성능 시뮬레이션)

  • Seo, Yong-Jin;Yang, Jun-Won
    • Journal of Satellite, Information and Communications
    • /
    • v.11 no.4
    • /
    • pp.27-32
    • /
    • 2016
  • A conventional double diffused drain n-type MOSFET (DDD_NMOS) device shows SCR behaviors with very low snapback holding voltage and latch-up problem during normal operation. However, a modified DDD_NMOS-based silicon controlled rectifier (DDD_NSCR_CPS) device with a counter pocket source (CPS) structure is proven to increase the snapback holding voltage and on-resistance compare to standard DDD_NSCR device, realizing an excellent electrostatic discharge protection performance and the stable latch-up immunity.

Improvement of ESD (Electrostatic Discharge) Protection Performance of NEDSCR (N-Type Extended Drain Silicon Controlled Rectifier) Device using CPS (Counter Pocket Source) Ion Implantation (CPS 이온주입을 통한 NEDSCR 소자의 정전기 보호 성능 개선)

  • Yang, Jun-Won;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
    • /
    • v.8 no.1
    • /
    • pp.45-53
    • /
    • 2013
  • An electrostatic discharge (ESD) protection device, so called, N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high voltage I/O applications. A conventional NEDSCR device shows typical SCR-like characteristics with extremely low snapback holding voltage. This may cause latch-up problem during normal operation. However, a modified NEDSCR device with proper junction/channel engineering using counter pocket source (CPS) ion implantation demonstrates itself with both the excellent ESD protection performance and the high latch-up immunity. Since the CPS implant technique does not change avalanche breakdown voltage, this methodology does not reduce available operation voltage and is applicable regardless of the operation voltage.

Study on the Optimal CPS Implant for Improved ESD Protection Performance of PMOS Pass Structure Embedded N-type SCR Device with Partial P-Well Structure (PMOS 소자가 삽입된 부분웰 구조의 N형 SCR 소자에서 정전기 보호 성능 향상을 위한 최적의 CPS 이온주입에 대한 연구)

  • Yang, Jun-Won;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
    • /
    • v.10 no.4
    • /
    • pp.1-5
    • /
    • 2015
  • The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW_PGM(primary gate middle) and optimal CPS(counter pocket source) implant demonstrate the stable ESD protection performance with high latch-up immunity.

Simulation-based P-well design for improvement of ESD protection performance of P-type embedded SCR device

  • Seo, Yong-Jin
    • Journal of IKEEE
    • /
    • v.26 no.2
    • /
    • pp.196-204
    • /
    • 2022
  • Electrostatic discharge (ESD) protection devices of P-type embedded silicon-controlled rectifier (PESCR) structure were analyzed for high-voltage operating input/output (I/O) applications. Conventional PESCR standard device exhibits typical SCR characteristics with very low-snapback holding voltages, resulting in latch-up problems during normal operation. However, the modified device with the counter pocket source (CPS) surrounding N+ source region and partially formed P-well (PPW) structures proposed in this study could improve latch-up immunity by indicating high on-resistance and snapback holding voltage.

Optimal P-Well Design for ESD Protection Performance Improvement of NESCR (N-type Embedded SCR) device (NESCR 소자에서 정전기 보호 성능 향상을 위한 최적의 P-Well 구조 설계)

  • Yang, Jun-Won;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
    • /
    • v.9 no.3
    • /
    • pp.15-21
    • /
    • 2014
  • An electrostatic discharge (ESD) protection device, so called, N-type embedded silicon controlled rectifier (NESCR), was analyzed for high voltage operating I/O applications. A conventional NESCR standard device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latch-up problem during normal operation. However, our modified NESCR_CPS_PPW device with proper junction/channel engineering such as counter pocket source (CPS) and partial P-well structure demonstrates highly latch-up immune current-voltage characteristics with high snapback holding voltage and on-resistance.

Improvement of Electrostatic Discharge (ESD) Protection Performance through Structure Modification of N-Type Silicon Controlled Rectifier Device (N형 실리콘 제어 정류기 소자의 구조 변형을 통한 정전기 보호성능의 향상에 대한 연구)

  • Yang, Jun-Won;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
    • /
    • v.8 no.4
    • /
    • pp.124-129
    • /
    • 2013
  • An electrostatic discharge (ESD) protection device, so called, N-type SCR with P-type MOSFET pass structure (NSCR_PPS), was analyzed for high voltage I/O applications. A conventional NSCR_PPS device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latch-up problem during normal operation. However, a modified NSCR_PPS device with counter pocket source(CPS) and partial p-type well(PPW) structure demonstrates highly latch-up immune current-voltage characteristics.

Effects of the ESD Protection Performance on GPNS(Gate to Primary N+ diffusion Space) Variation in the NSCR_PPS Device (NSCR_PPS 소자에서 게이트와 N+ 확산층 간격의 변화가 정전기 보호성능에 미치는 영향)

  • Yang, Jun-Won;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
    • /
    • v.10 no.4
    • /
    • pp.6-11
    • /
    • 2015
  • The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different GPNS(Gate to Primary $N^+$ Diffusion Space) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device with FPW(Full P-Well) structure and non-CPS(Counter Pocket Source) implant shows typical SCR-like characteristics with low on-resistance(Ron), low snapback holding voltage(Vh) and low thermal breakdown voltage(Vtb), which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW(Partial P-Well) structure and optimal CPS implant demonstrate the improved ESD protection performance as a function of GPNS variation. GPNS was a important parameter, which is satisfied design window of ESD protection device.

Optimal Design of ESD Protection Device with different Channel Blocking Ion Implantation in the NSCR_PPS Device (NSCR_PPS 소자에서 채널차단 이온주입 변화에 따른 최적의 정전기보호소자 설계)

  • Seo, Yong-Jin;Yang, Jun-Won
    • Journal of Satellite, Information and Communications
    • /
    • v.11 no.4
    • /
    • pp.21-26
    • /
    • 2016
  • The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different implant of channel blocking region was discussed for high voltage I/O applications. A conventional NSCR standard device shows low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified channel blocking structure demonstrate the improved ESD protection performance as a function of channel implant variation. Therefore, the channel blocking implant was a important parameter. Since the modified device with CPS_PDr+HNF structure satisfied the design window, we confirmed the applicable possibility as a ESD protection device for high voltage operating microchips.

Effects on the ESD Protection Performance of PPS(PMOS Pass Structure) Embedded N-type Silicon Controlled Rectifier Device with different Partial P-Well Structure (PPS 소자가 삽입된 N형 SCR 소자에서 부분웰 구조가 정전기 보호 성능에 미치는 영향)

  • Yang, Jun-Won;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
    • /
    • v.9 no.4
    • /
    • pp.63-68
    • /
    • 2014
  • Electrostatic Discharge(ESD) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW demonstrate the stable ESD protection performance with high latch-up immunity.