• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.1
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• pp.90-97
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• 2019

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.1 s.116
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• pp.90-95
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• 2007

Chaotic OOK(On-Off Keying) modulation method can be used in LDR(Low Data Rate) UWB systems. The chaotic generator in one of the most important circuit in this system. The traditional chaotic generator circuits using analog feed back technique have low yield characteristic due to the process variation. A novel quasi-chaotic signal generator using digital PN-sequence in proposed in this paper and verified in 0.18um CMOS teleology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.906-909
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• 2006

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.2
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• pp.139-145
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• 2024

This paper presents the design of a voltage controlled oscillator (VCO) which is one of the key building blocks in modern wireless communication systems with small VCO gain (K_vco) variation. To compensate conventional large K_vco variation, a series varactor bank has been added to the conventional LC-tank with parallel capacitor bank array. And also, in order to achieve excellent phase noise performance while maintaining wide tuning range, a mixed coarse/fine tuning scheme(series varactor array and parallel capacitor array) is chosen. The switched varactor array bank is controlled by the same digital code for switched capacitor array without additional digital circuits. For use at a low voltage of 1.2V, the proposed current reference circuit in this paper used a current reference circuit for safety with the common gate removed more safely. Implemented in a TSMC 0.13㎛ CMOS RF technology, the proposed VCO can be tuned from 4.4GH to 5.3GHz with the K_vco (VCO gain ) variation of less than 9.6%. While consuming 3.1mA from a 1.2V supply, the VCO has -120dBc/Hz phase noise at 1MHz offset from the carrier of the 5.3 GHz.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.271-274
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• 1999

This paper proposes a simple architecture of digital dividing block in dual-modulus prescaler phase-locked loop used in the wireless communication. Proposed architecture eliminates a swallow counter in the conventional one and demonstrates the advantages in reducing the power consumption and the gate-counts. Therefore, it is suitable for small die area and low power applications. The circuit is designed in a standard 0.35${\mu}{\textrm}{m}$ CMOS process.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.195-198
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• 2000

It is possible to perform the digital fuzzy logical high-speed and high-precision computation by the use of redundantly-represented binary positive-digit number arithmetic operation. In this paper, as basic operation circuits in the fuzzy logic new voltage-mode 4-valued binary parallel processing operation circuits using positive redundantly-expressed binary-coded numbers is discussed.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.135-144
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• 2003

This work proposes on-chip full CMOS current and voltage references for high-speed mixed-mode circuits. The proposed current reference circuit uses a digital-domain calibration method instead of a conventional analog calibration to obtain accurate current values. The proposed voltage reference employs internal reference voltage drivers to minimize the high-frequency noise from the output stages of high-speed mixed-mode circuits. The reference voltage drivers adopt low power op amps and small- sized on-chip capacitors for low power consumption and small chip area. The proposed references are designed, laid out, and fabricated in a 0.18 um n-well CMOS process and the active chip area is 250 um x 200 um. The measured results show the reference circuits have the power supply variation of 2.59 %/V and the temperature coefficient of 48 ppm/$^{\circ}C$ E.

• Journal of IKEEE
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• v.14 no.3
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• pp.232-235
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• 2010

A 60GHz active phase shifter with 65nm CMOS is presented by replacing passive switches in switched-line type phase shifter with active ones. Active-switch phase shifter is composed of active-switch blocks and passive delay network blocks. The active-switch phase shifter design is compact compare with the conventional vector-sum phase shifter. Active-switch blocks are designed to accomplish required input and output impedances whose requirements are different whether the switch is on or off. And passive delay network blocks are composed of lumped L,C instead of normal microstrip line to reduce the size of the circuit. An 1-bit phase shifter is fabricated by TSMC 65nm CMOS technology and measurement results present -4dB average insertion loss and 120 degree phase shift at 65GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.225-228
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• 2012

In this paper, a 10-bit digital-to-analog converter (DAC) with small area is proposed. The 10-bit DAC consists of a 8-bit decoder, a 2-bit time-interpolator, and a buffer amplifier. The proposed time-interpolation is achieved by controlling the charging time through a low-pass filter composed of a resistor and a capacitor. To implement the accurate time-interpolator, a control pulse generator using a replica circuit is proposed to minimize the effect of the process variation. The proposed 10-bit Time-Interpolation DAC occupies 61 % of the conventional 10-bit resistor-string DAC. The proposed DAC is designed using a $0.35{\mu}m$ CMOS process with a 3.3 V supply. The simulated DNL and INL are +0.15/-0.21 LSB and +0.15/-0.16 LSB, respectively.