Browse > Article

On-Chip Full CMOS Current and Voltage References for High-Speed Mixed-Mode Circuits  

Cho, Young-Jae (Dept. of Electronic Engineering, Sogang University)
Bae, Hyun-Hee (Dept. of Electronic Engineering, Sogang University)
Jee, Yong (Dept. of Electronic Engineering, Sogang University)
Lee, Seung-Hoon (Dept. of Electronic Engineering, Sogang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.40, no.3, 2003 , pp. 135-144 More about this Journal
Abstract
This work proposes on-chip full CMOS current and voltage references for high-speed mixed-mode circuits. The proposed current reference circuit uses a digital-domain calibration method instead of a conventional analog calibration to obtain accurate current values. The proposed voltage reference employs internal reference voltage drivers to minimize the high-frequency noise from the output stages of high-speed mixed-mode circuits. The reference voltage drivers adopt low power op amps and small- sized on-chip capacitors for low power consumption and small chip area. The proposed references are designed, laid out, and fabricated in a 0.18 um n-well CMOS process and the active chip area is 250 um x 200 um. The measured results show the reference circuits have the power supply variation of 2.59 %/V and the temperature coefficient of 48 ppm/$^{\circ}C$ E.
Keywords
CMOS; high speed; mixed mode; current reference; voltage reference;
Citations & Related Records
연도 인용수 순위
  • Reference
1 R. A. Blauschild, P. A. Tucci, R. S. Muller, and R. G. Meyer, 'A New NMOS Temperature-stable Voltage Reference,' IEEE J Solid-State Circuits, vol. SC-13, pp. 767-773, Dec. 1978   DOI
2 H. J. Oguey and B. Gerber, 'MOS Voltage Reference Based on Polysilicon Gate Work Function Difference,' IEEE J. Solid-State Circuits, vol. SC-15, pp, 264-269, June 1980   DOI
3 T. Furuyama, Y. Watanabe, T. Oshawa, and S. Watanabe, 'A New On Chip Voltage Converter for Submicrometer High-Density DRAM's,' IEEE J. Solid-State Circuits, vol. SC-22, pp. 437-441. June 1987   DOI
4 K. Itoh, 'Trend in Megabit DRAM Circuit Design,' IEEE J. Solid-State Circuits, vol. 25, pp. 778-789, June 1990   DOI   ScienceOn
5 H. J. Song and C. K. Kim, 'A Temperature-Stabilized SOL Voltage Reference Based on Threshold Voltage Difference Between Enhancement Depletion NMOSFET' s,' IEEE J. Solid-State Circuits, vol. SC-28, pp, 671-677, June 1993   DOI   ScienceOn
6 K. Khanoyan, F. Behbahani, and A. A. Abidi, 'A 10b, 400 MS/s Glitch-Free CMOS D/A Converter,' in Symp. VLSI Circuits Dig. Tech. Papers, June 1999, pp. 73-76   DOI
7 L. Singer, S. Ho, M. Timko, and D. Kelly, 'A 12b 65MSample/s CMOS ADC with 82dB SFDR at 120MHz,' in ISSCC Dig. Tech. Papers, pp. Feb. 2000, pp. 38-39   DOI
8 A. M. Abo and P. R. Gray, 'A 1.5-V, 10-bit, 14.3-MSample/s CMOS Pipeline Analog-to-Digital Converter,' IEEE J. Solid-State Circuits, vol. SC-34, pp, 599-606, May 1999   DOI   ScienceOn
9 S. H. Lee and Y. Jee, 'A Temperature and Supply-Voltage Insensitive CMOS Current Reference,' IEICE Trans. Electron. vol. E82-C, pp. 1552-1556, Aug. 1999
10 S. H. Lewis and P. R. Gray, 'A Pipelined 5-MSample/s 9-bit Analog-to-Digital Converter,' IEEE J. Solid-State Circuits, vol. SC22, pp. 954-961, Dec. 1987   DOI
11 B. S. Song and P. R. Gray, 'A Precision Curvature-Compensated CMOS Bandgap Reference,' IEEE J. Solid-State Circuits, vol. SC-18, pp. 634-643, Dec. 1983   DOI