Simple Dividing Architecture of Dual-Modulus Prescaler Phase-Locked Loop for Wireless Communication

무선 통신용 Dual-Modulus Prescaler 위상고정루프(PLL)의 간단한 분주 구조

This paper proposes a simple architecture of digital dividing block in dual-modulus prescaler phase-locked loop used in the wireless communication. Proposed architecture eliminates a swallow counter in the conventional one and demonstrates the advantages in reducing the power consumption and the gate-counts. Therefore, it is suitable for small die area and low power applications. The circuit is designed in a standard 0.35${\mu}{\textrm}{m}$ CMOS process.