• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.8
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• pp.9-16
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• 2000

MOS transistors are fabricated and evaluated for RF IC applications such as mobile communication systems using 0.35m CMOS process. Characteristics of MOSFETs are analyzed at various channel length, width and bias conditions. From the analysis, cut-off frequency ($f_T$) is independent on channel width but maximum oscillation frequency ($f_{max}$) tends to derease as the channel width increases. As channel length increases, $f_T$ and fmax decrease. $f_T$ is 22GHz and fmax is 28GHz at its maximum value. High frequency noise performance is improved with larger channel width and smaller channel length at same bias conditions. NFmin at 2GHz is 0.45dB as a minimum value. From the evaluation, MOSFETs designed using 0.35m CMOS process demonstrated a full potential for the commercial RF ICs for mobile communication systems near 2GHz. And optimization methods of the CMOS transistors for RF applications are presented in this paper.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.5
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.60-68
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• 2000

This paper describes a design methodology for the CMOS current source which can be implemented in standard memory process. The proposed techniques provide a good characteristic against the power-supply variation by utilizing a self-bias circuit and the reduction of the first-order component of the temperature variation through the new temperature compensation technique and include a new current-sensing start-up circuit enabling a robust operation against the voltage noise generated during the operation of the chip. In addition to the circuit-design technology, techniques where the proposed CMOS current-reference circuit can be applied to the clocking circuits of a very high-speed DRAM are presented. The feasibility of the suggested design methodology for the CMOS current reference is demonstrated by both the analytical method and the circuit simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.383-390
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• 2014

This paper presents an excitatory CMOS neuron oscillator circuit design, which can synchronize two neuron-bursting patterns. The excitatory CMOS neuron oscillator is composed of CMOS neurons and CMOS excitatory synapses. And the neurons and synapses are connected into a close loop. The CMOS neuron is based on the Hindmarsh-Rose (HR) neuron model and excitatory synapse is based on the chemical synapse model. In order to fabricate using a 0.18 um CMOS standard process technology with 1.8V compatible transistors, both time and amplitude scaling of HR neuron model is adopted. This full-chip integration minimizes the power consumption and circuit size, which is ideal for motion control unit of the proposed bio-mimetic micro-robot. The experimental results demonstrate that the proposed excitatory CMOS neuron oscillator performs the expected waveforms with scaled time and amplitude. The active silicon area of the fabricated chip is $1.1mm^2$ including I/O pads.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.1-8
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• 2005

A $0.35\mu$m SiGe BiCMOS fabrication process has been timely developed, which is aiming at wireless RF ICs development and fast growing SiGe RF market. With non-selective SiGe epilayer, SiGe HBTs in this process used trapezoidal Ge base profile for the enhanced AC performance via Ge induced bandgap niuoin. The characteristics of hFE 100, $f_{T}\;45GHz,\;F_{max}\;50GHz,\;NF_{min}\;0.8dB$ have been obtained by optimizing not only SiGe base profile but also RTA condition after emitter polysilicon deposition, which enables the SiGe technology competition against the worldwide cutting edge SiGe BiCMOS technology. In addition, the process incorporates the CMOS logic, which is fully compatible with $0.35\mu$m pure logic technology. High Q passive elements are also provided for high precision analog circuit designs, and their quality factors of W(1pF) and inductor(2nH) are 80, 12.5, respectively.

• Journal of the Korean Vacuum Society
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• v.14 no.1
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• pp.29-34
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• 2005

The degradation of the SiGe hetero-junction bipolar transistor(HBT) properties in SiGe BiCMOS process was investigated in this paper. The SiGe HBT prepaired by SiGe BiCMOS process, unlike the conventional one, showed the degraded DC characteristics such as the decreased Early voltage, the decreased collector-emitter breakdown voltage, and the highly increased base leakage current. Also, the cutoff frequency(f/sub T/) and the maximum oscillation frequency(f/sub max/) representing the AC characteristics are reduced to below 50%. These deteriorations are originated from the change of the locations of emitter-base and collector-base junctions, which is induced by the variation of the doping profile of boron in the SiGe base due to the high-temperature source-drain annealing. In the result, the junctions pushed out of SiGe region caused the parastic barrier formation and the current gain decrease on the SiGe HBT device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.59-64
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• 2006

The slope of the ramp generator in a single slope ADC(analog-to-digital converter) suffers from process and frequency variation. This variation in ramp slope causes ADC gain variation and eventually limits the performance of the ISP(image signal processing) in a CIS(CMOS image sensor) that uses the single slope ADC. This paper proposes a ramp slope BISC(built-in-self-calibration) scheme for CIS. The CIS with proposed BISC was fabricated with a $0.35{\mu}m$ process. The measurement results show that the proposed architecture effectively calibrate the ramp slope against process and clock frequency variation. The silicon area overhead is less than $0.7\%$ of the full chip area.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.226-235
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• 1999

To investigate SPICE noise model and the behavior of its parameters, 1/f noise of NMOS devices fabricated by BiCMOS process is measured and compared to the various noise models and measured results. For the long channel devices, bias dependence of the drain current noise power spectral density $S_{Id}$ of NMOS is similar to the previous results. Equivalent gate noise power spectral density $S_{Vg}$ shows weak dependence on the gate and drain voltages in long channel NMOS as the previous results. However, it is shown that most of published noise models are difficult to apply to short channel devices. Therefore, in this study, with comparison of our experimental results, we have tried to find the model of 1/f noise, appropriate for our NMOS device fabricated by BiCMOS process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.22-28
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• 1998

A $g_m$-control technique using a new electronic zener diode (EZD) for CMOS rail-torail input stages is presented. A regulated CMOS inverter is used as an EZD to obtain a constant-$g_m$ input stage. The turn-off characteristic of the proposed EZD is better than that of the existing EZD using two complementarey diodes, and thus, better $g_m$-control can be achieved. With this input stage, a 3V constant-$g_m$ rail-to-rail CMOS op-amp has been designed and fabricated using a $0.8\mu\extrm{m}$single-poly, double-metal CMOS process. Measurements results show that the $g_m$ variation is about 6% over the entire input common-mode range, and the op-amp has a dc gain of 88dB and a unity-gain frequency of 4MHz for $C_L=20pF, R_L=10k\Omega$

• The Journal of the Acoustical Society of Korea
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• v.19 no.1
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• pp.84-88
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• 2000

In this paper, a low voltage CMOS analog four-quadrant multiplier is presented. The proposed multiplier is composed of two fully differential transconductors and lowers supply voltage down to VT+2VDS,sat+VDS,triode. The designed analog four-quadrant multiplier has simulated by HSPICE using 0.25㎛ n-well CMOS process with a 1.2V supply voltage. Simulation results show that the THD can be 1.28% at maximum differential input of 0.7VP-P.