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A Single-Slope Column-ADC using Ramp Slope Built-In-Self-Calibration Scheme for a CMOS Image Sensor  

Ham Seog-Heon (Dept. Electrical and Electronic Engineering, Yonsei Univ.)
Han Gunhee (Dept. Electrical and Electronic Engineering, Yonsei Univ.)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.1, 2006 , pp. 59-64 More about this Journal
Abstract
The slope of the ramp generator in a single slope ADC(analog-to-digital converter) suffers from process and frequency variation. This variation in ramp slope causes ADC gain variation and eventually limits the performance of the ISP(image signal processing) in a CIS(CMOS image sensor) that uses the single slope ADC. This paper proposes a ramp slope BISC(built-in-self-calibration) scheme for CIS. The CIS with proposed BISC was fabricated with a $0.35{\mu}m$ process. The measurement results show that the proposed architecture effectively calibrate the ramp slope against process and clock frequency variation. The silicon area overhead is less than $0.7\%$ of the full chip area.
Keywords
Built-in-self-calibration; CMOS image sensor; Ramp generator; Single-slope analog-to-digital converter;
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