• Journal of Navigation and Port Research
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• v.31 no.9
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• pp.759-762
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• 2007

A novel miniaturized CMOS C-Band bandpass filter based on diagonally end-shorted coupled lines and interdigital capacitors is proposed. The utilized coupled lines structure reduced the configuration in size, as small as a few degrees. Moreover, the characteristic of interdigital capacitor, relatively high Q and good capacitance tolerance, accounts for the satisfied performance of this new filter. A two-stage bandpass filter was designed and fabricated with chip surface area only $1.02{\times}1.4\;mm^2$.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2567-2569
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• 2001

본 논문에서는 내이(Inner ear)의 한 부분을 차지하는 Inner Hair Cell을 구현함에 있어 필수적인 요소인 낮은 극점을 갖는 저역통과필터(LPF)를 최소의 면적으로 구현하기 위한 설계방법을 언급한다. 이를 위해 본 논문에서는 CMOS Compatible Lateral BJT (CLBT)를 사용하여 능동소자의 등가 저항을 증가시켜 커패시터의 값을 획기적으로 줄일 수 있는 기법의 LPF와 gm-C필터를 이용한 LPF를 전류모드로 설계하였다. 저전력 특성과 큰 임피던스 특성을 얻기 위해 모든 트랜지스터는 약반전 영역에서 동작하고 극점은 1kHz근처에 존재한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.201-202
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• 2005

The electrical characteristics of high-voltage LDMOSFET (Lateral Double-diffused MOSFET) fabricated by a CMOS technology were investigated depending on the process and design parameters. The off-state breakdown voltages of n-channel LDMOSFETs were linearly increased with increasing to the drift region length. For the case of decreasing n-well ion implant doses from $1.0\times10^{13}/cm^2$ to $1.0\times10^{12}/cm^2$, the off-state breakdown voltage was increased approximately two times, however, the on-resistance was also increased about 76%. Moreover, the on- and off-state breakdown voltages were also linearly increased with increasing the channel to n-tub spacing due to the reduction of impact ionization at the drift region.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2006.11a
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• pp.145-148
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• 2006

본 논문은 $0.35{\mu}m$ 2중 폴리 CMOS 공정을 이용하여 프리만 신경회로 모델의 기본 요소가 되는 입력 취합 블록과 필드 앤드 홀드 방식의 2차 저역 통과 필터의 구현 및 부궤환과 비대칭 트랜스 콘덕터로 이루어지는 비선형 함수 블록을 설계하고 SPICE 회로 모의실험을 통해 결과를 확인하였다.

• ETRI Journal
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• v.44 no.5
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• pp.837-848
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• 2022

Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified grey-wolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.254-259
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• 1987

This paper describes the CMOS standard cell library implemented in double metal single poly gate process with 3\ulcornerm design rule, and its results of testing. This standard cell library contains total 33 cells of random logic gates, flip-flop gates and input/output buffers. All of cell was made to have the equal height of 98\ulcornerm, and width in multiple constant grid of 9 \ulcornerm. For cell data base, the electric characteristics of each cell is investigated and delay is characterized in terms of fanout. As the testing results of Ring Oscillator among the cell library, the average delay time for Inverter is 1.05 (ns), and the delay time due to channel routing metal is 0.65(ps)per unit length.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.12
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• pp.5832-5837
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• 2011

In this paper, we designed a thermal shutdown block for LED applications using a 1 ${\mu}m$ CMOS process. The proposed thermal shutdown protection circuit has been designed with a shut-off temperature of $120^{\circ}C$ and a restart temperature of $90^{\circ}C$ which are suitable conditions for LED driver IC. Also, we got SPICE simulation results of the circuit about process variation of the semiconductor fabrication. From simulation data, process variation rate of the proposed circuit are within 7 % which are good results compared with conventional BJT current mirror type circuit. Finally, we confirmed that the thermal shutdown circuit has good thermal protection function within a LED driver IC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.60-68
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• 2007

A technique is presented to extract differential second harmonic output from common source nodes of a cross-coupled P-& N-FET oscillator. Provided the impedances at the common source nodes are optimized and the fundamental swing at the VCO core stays in a proper mode, it is found that the amplitude and phase errors can be kept within $0{\sim}1.6dB$ and $+2.2^{\circ}{\sim}-5.6^{\circ}$, respectively, over all process/temperature/voltage corners. Moreover, an impedance-tuning circuit is proposed to compensate any unexpectedly high errors on the differential signal output. A Prototype 5-GHz VCO with a 2.5-Hz LC resonator is implemented in $0.18-{\mu}m$ CMOS. The error signal between the differential outputs has been measured to be as low as -70 dBm with the aid of the tuning circuit. It implies the push-push outputs are satisfactorily differential with the amplitude and phase errors well less than 0.34 dB and $1^{\circ}$, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.58-65
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• 2015

This paper presents the design of an implantable stimulation IC intended for neural prosthetic devices using $0.18-{\mu}m$ standard CMOS technology. The proposed single-channel biphasic current stimulator prototype is designed to deliver up to 1 mA of current to the tissue-equivalent $10-k{\Omega}$ load using 12.8-V supply voltage. To utilize only low-voltage standard CMOS transistors in the design, transistor stacking with dynamic gate biasing technique is used for reliable operation at high-voltage. In addition, active charge balancing circuit is used to maintain zero net charge at the stimulation site over the complete stimulation cycle. The area of the total stimulator IC consisting of DAC, current stimulation output driver, level-shifters, digital logic, and active charge balancer is $0.13mm^2$ and is suitable to be applied for multi-channel neural prosthetic devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.45-51
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• 2009

A low-voltage, low-power analog CMOS front-end for a cardiac pacemaker is proposed. The circuits include a 4th order switched-capacitor (SC) filter with a passband of 80-120 Hz and a SC variable gain amplifier whose control range is from 0 to 24-dB with 0.094 dB step. An inverter-based switched-capacitor circuit technique is used for low-voltage operation and ultra-low power consumption, and correlated double sampling technique is used for reducing the finite gain effect of an inverter. The proposed circuit has been designed in a $0.35-{\mu}m$ CMOS process, and it achieves 80-dB SFDR at 5-kHz sampling frequency. The power consumption is only 330 nW at 1-V power supply.