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http://dx.doi.org/10.5573/ieie.2015.52.5.058

A High-Voltage Compliant Neural Stimulation IC for Implant Devices Using Standard CMOS Process  

Abdi, Alfian (Dept. of Electrical and Information Engineering, Seoul National University of Science and Technology)
Cha, Hyouk-Kyu (Dept. of Electrical and Information Engineering, Seoul National University of Science and Technology)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.52, no.5, 2015 , pp. 58-65 More about this Journal
Abstract
This paper presents the design of an implantable stimulation IC intended for neural prosthetic devices using $0.18-{\mu}m$ standard CMOS technology. The proposed single-channel biphasic current stimulator prototype is designed to deliver up to 1 mA of current to the tissue-equivalent $10-k{\Omega}$ load using 12.8-V supply voltage. To utilize only low-voltage standard CMOS transistors in the design, transistor stacking with dynamic gate biasing technique is used for reliable operation at high-voltage. In addition, active charge balancing circuit is used to maintain zero net charge at the stimulation site over the complete stimulation cycle. The area of the total stimulator IC consisting of DAC, current stimulation output driver, level-shifters, digital logic, and active charge balancer is $0.13mm^2$ and is suitable to be applied for multi-channel neural prosthetic devices.
Keywords
neural stimulation; active charge balancing; transistor stacking; dynamic biasing; high-voltage;
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