Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 1V Analog CMOS Front-End for Cardiac Pacemaker Applications

심장박동 조절장치를 위한 1V 아날로그 CMOS 전단 처리기

  • Chae, Young-Cheol (Department of Electrical and Electronic Eng., Yonsei University) ;
  • Lee, Jeong-Whan (Department of Electrical and Electronic Eng., Yonsei University) ;
  • Lee, In-Hee (Department of Electrical and Electronic Eng., Yonsei University) ;
  • Han, Gun-Hee (Department of Electrical and Electronic Eng., Yonsei University)
  • 채영철 (연세대학교 전기.전자공학과) ;
  • 이정환 (연세대학교 전기.전자공학과) ;
  • 이인희 (연세대학교 전기.전자공학과) ;
  • 한건희 (연세대학교 전기.전자공학과)
  • Published : 2009.01.25
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Abstract

A low-voltage, low-power analog CMOS front-end for a cardiac pacemaker is proposed. The circuits include a 4th order switched-capacitor (SC) filter with a passband of 80-120 Hz and a SC variable gain amplifier whose control range is from 0 to 24-dB with 0.094 dB step. An inverter-based switched-capacitor circuit technique is used for low-voltage operation and ultra-low power consumption, and correlated double sampling technique is used for reducing the finite gain effect of an inverter. The proposed circuit has been designed in a $0.35-{\mu}m$ CMOS process, and it achieves 80-dB SFDR at 5-kHz sampling frequency. The power consumption is only 330 nW at 1-V power supply.

심장박동 조절장치를 위한 저전압 저전력 전단 처리기를 제안한다. 제안된 회로는 80 Hz에서 120 Hz의 대역폭을 가지는 4차의 스위치드 커패시터 필터와 0 dB에서 24 dB까지 0.094 dB 간격으로 전압이득의 조절이 가능한 전압증폭기를 구현하였다. 낮은 전압에서 동작하고, 전력소모를 극소화하기 위해서 인버터 기반의 스위치드 커패시터 회로를 사용하였으며, 인버터가 가지는 작은 전압이득을 보상하기 위해서 상호상관 기법을 사용하였다. 제안된 회로는 $0.35-{\mu}m$ CMOS 공정을 이용하여 구현되었으며, 5kHz의 샘플링 주파수에서 80-dB의 SFDR을 가진다. 이때 전력소모는 1 V의 전원전압에서 330 nW에 불과하다.

Keywords

References

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