• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.54-59
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• 2008

A highly accurate wide swing BiCMOS cascode current mirror is proposed. It uses the base-current compensated BJT current mirror. It increases both output impedance and output voltage range by using the npn-NMOS cascode instead of the NMOS-NMOS cascode. The npn transistor copies the input current and the NMOS transistor increases the output impedance for the accurate current mirroring. The proposed current mirror achieves highly constant current for wide output voltage range. Simulation results were verified with measurements performed on a fabricated chip using a 5/16V 0.5um BCD process. It has only $-2.5%{\sim}1.0%$ current error for $0.3V{\sim}16V$ output voltage range.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.877-882
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• 2016

In this paper, a novel CMOS high Q factor 2-port active inductor has been proposed. The proposed circuit is designed by cascading basic gyrator-C structural active inductors and attaching the feedback LC resonance circuit. This LC resonator can compensate parasitic capacitance of transistor and can improve Q factor over wide frequency range. The proposed circuit was fabricated and simulated using 65 nm Samsung RF CMOS process. The fabricated circuit shows inductance of above 2 nH and Q factor higher than 40 in the frequency range of 1~6 GHz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.27-37
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• 1999

A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.117-122
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• 2006

A CMOS LNA based on a single-stage cascode configuration is designed for MB-OFDM ultra-wide band(UWB) systems. Wideband($3.1GHz\~4.9GHz$) input matching is performed using a simple bandpass filter to minimize the chip size and the noise figure degradation. The simulation results using $0.18{\mu}m$ CMOS process parameters show a power gain of 9.7dB, a 3dB band width of $2.1GHz\~7.1GHz$, a minimum NF of 2dB, an IIP3 of -2dBm. better than -11.8dB of input matching while occupying only $0.74mm^2$ of chip area. It consumes 25.8mW from a 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.135-144
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• 2003

This work proposes on-chip full CMOS current and voltage references for high-speed mixed-mode circuits. The proposed current reference circuit uses a digital-domain calibration method instead of a conventional analog calibration to obtain accurate current values. The proposed voltage reference employs internal reference voltage drivers to minimize the high-frequency noise from the output stages of high-speed mixed-mode circuits. The reference voltage drivers adopt low power op amps and small- sized on-chip capacitors for low power consumption and small chip area. The proposed references are designed, laid out, and fabricated in a 0.18 um n-well CMOS process and the active chip area is 250 um x 200 um. The measured results show the reference circuits have the power supply variation of 2.59 %/V and the temperature coefficient of 48 ppm/$^{\circ}C$ E.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.17-22
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• 2006

CMOS LC VCO with fast response adaptive frequency calibration (AFC) technique for IEEE 802.11a/b/g WLANs is designed in 1.8V $0.18{\mu}m$ CMOS process. The possible operation is verified for 5.8GHz band, 5.2GHz band, and 2.4GHz band using the switchable L-C resonators. To linearize its frequency-voltage gain (Kvco), optimized multiple MOS varactor biasing tecknique is used. In order to operate in each band frequency range with reduced VCO gain, 4-bit digitally controlled switched- capacitor bank is used and a wide-range digital logic quadricorrelator (WDLQ) is implemented for fast frequency detector.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.8
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• pp.1465-1470
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• 2006

This paper presents a design of low power CMOS LNA(Low Noise Amplifier) for 2.4 GHz ZigBee applications that is a promising international standard for short area wireless communications. The proposed circuit has been designed using TSMC $0.18{\mu}m$ CMOS process technology and two stage cascade topology by current reuse technique. Two stage cascade amplifiers use the same bias current in the current reused stage which leads to the reduction of the power dissipation. LNA design procedures and the simulation results using ADS(Advanced Design System) are presented in this paper. Simulation results show that the LNA has a extremely low power dissipation of 1.38mW with a supply voltage of 1.0V. This is the lowest value among LNAs ever reported. The LNA also has a maximum gain of 13.38dB, input return loss of -20.37dB, output return loss of -22.48dB and minimum noise figure of 1.13dB.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.38-47
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• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.65-73
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• 2007

This paper presents a low power CMOS continuous-time $\Sigma\Delta$ (sigma-delta) modulator for UMTS receivers. The loop filter of the continuous-time $\Sigma\Delta$ modulator consists of an active-RC filter which performs high linearity characteristics and has a simple tuning circuit for low power operating system The architecture of this modulator is the $3^{rd}-order$ 4-bit single loop configuration with a 24 of OSR (Oversampling Ratio) to increase the power efficiency. The modulator includes a half delay feedback path to compensate the excess loop delay. The experimental results of the modulator are 71dB, 65dB and 74dB of the peak SNR, peak SMR and dynamic range, respectively. The continuous-time $\Sigma\Delta$ modulator is fabricated in a 0.18-um 1P4M CMOS standard process and dissipates 15mW for a single supply voltage of 1.8V.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.59-65
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• 2014

In this paper, in order to improve efficiency performance of power amplifiers, a mode changeable autotransformer is proposed. Efficiency performance at the low-power mode can be improved by adopting the mode changeable autotransformer. A dual-mode autotransfomrer CMOS power amplifier using a standard 0.18-${\mu}m$ CMOS process is designed in this work. Number of turns in a primary winding is re-configurated according to mode change between the high-power mode and the low-power mode. Thus, the efficiency performance of the power amplifier at each mode is optimized. EM and total circuit simulation results verify that low-power mode power added efficiency(PAE) at 24dBm output power is improved from 10.4% to 26.1% using the proposed multi-mode operation.