• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.425-428
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• 1998

In this work, single-poly EEPROM has been designed and fabricated by using standard 0.8.mu.m CMOS process. The initial threshold voltage was aobut 0.8V but it increased ot about 6.5V after programming at Vds=11.5V and Vcg=6.5V. After erasing devices at Vs=14.2V, the threshold voltage decreased to about 1.5V. The programming time and erasing trime wree about 6ms. and 100ms. respectively. The erasing time can be reduced by applying a series of shorter erase pulse s instead of a long single erase pulse.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.18-23
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• 2012

We propose and implement a single-wire communication protocol for thermal management systems using thin film thermoelectric modules for 3D IC cooling. The proposed single-wire communication protocol connects the temperature sensors, located near hot spots, to measure the local temperature of the chip. A unique ID number identifying the location of each hot spot is assigned to each temperature sensor. The prototype chip was fabricated by a $0.13{\mu}m$ CMOS MPW process, and the operation of the chip is verified.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.227-234
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• 2014

A transceiver for a high-speed inductive-coupling link is proposed. The bi-phase modulation (BPM) signaling scheme is used due to its good noise immunity. The transmitter utilizes a complementary switching method to remove glitches in transmitted data. To increase the timing margin on the receiver side, an integrating receiver with a pre-charging equalizer is employed. The proposed transceiver was implemented via a 130-nm CMOS process. The measured timing window for a $10^{-12}$ bit error rate (BER) at 1.8 Gb/s was 0.33 UI.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.198-201
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• 2014

The phase frequency detector (PFD) is one of the most important building blocks of a phase locked Loop (PLL). Due to blind-zone problem, the detection range of the PFD is low. The blind zone of a PFD directly depends upon the reset time of the PFD and the pre-charge time of the internal nodes of the PFD. Taking these two parameters into consideration, a PFD is designed to achieve a small blind zone closer to the limit imposed by process-voltage-temperature variations. In this paper an enhanced architecture is proposed for dynamic logic PFD to minimize the blind-zone problem. The techniques used are inverter sizing, transistor reordering and use of pre-charge transistors. The PFD is implemented in 180 nm technology with supply voltage of 1.8 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.582-594
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• 2016

Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm for code-based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS '89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.615-623
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• 2016

The paper describes a hysteretic buck converter including a differentiator and an adaptive hysteresis window controller. Differentiating the feedback signal achieves ultra-fast switching of the buck converter. The adaptive hysteresis window control allows a monotonous operation with predictable noise spectrum, and gives way to efficient design for variable supply and output voltages. The measurement results in a $0.13-{\mu}m$ CMOS process indicated that the switching frequency became double times higher, and the voltage ripple was reduced by up to 69%. They also indicated that the normalized switching frequency variation was reduced by 74% with variable $V_{DD}$ and by 63% with variable $V_{OUT}$. The power efficiency was improved by 3.5% depending on loading condition.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.42-47
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• 2017

This paper proposes a new series-coupled voltage-controlled oscillator (VCO). The proposed VCO consists of four current-reuse Armstrong VCOs (CRA-VCOs) coupled by four transformers. The series-coupling, current-reuse, and Armstrong topologies improve the phase noise performance by increasing the negative-Gm of the VCO core with half the current consumption of a conventional differential VCO. The proposed VCO consumes 6.54 mW at 9.78 GHz from a 1-V supply voltage. The measured phase noise is -115.1 dBc/Hz at an offset frequency of 1 MHz, and the FoM is -186.5 dBc/Hz. The frequency tuning range is from 9.38-10.52 GHz. The core area is $0.49mm^2$ in a $0.13-{\mu}m$ CMOS process.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1305-1308
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• 2008

In this study, we redesigned the reliable integrated on-panel display gate driver that was equipped with dual pull-down as well as controlled discharge-path structure to reduce the high voltage stress effect and realized with TSMC 0.35 um CMOS-based technology before. An improved discharge path and a low noise design are proposed for our new a-Si TFT process implementation. Our novel reliable gate driver design can make each cell of shift register to be insensitive to the coupling noise of that stage.

• Journal of the Korean Ceramic Society
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• v.41 no.4
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• pp.273-276
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• 2004

Report ferroelectric memories based on 0.35$\mu\textrm{m}$ CMOS technology ensuring ten-year retention and imprint at 175$^{\circ}C$. This excellent reliability resulted from newly developed BT-based ferroelectric films with superior reliability performance at high temperatures, and also resulted from robust integration schemes free from ferroelectric degradation due to process impurities such as moisture and hydrogen. The superior reliabilities at high temperature of ferroelectric memories using BT-based films are due to the random orientation by special bake treatments.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.121-124
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• 2009

In this paper, the techniques and design focus of flexible gain coltrol of LAN(Low Noise Amplifier) using the TSMC 0.18um CMOS process. The design frequency set up a standard on 2.4GHz that is used in Zigbee system. The design concepts a basic Cascode LNA techniques and a swiching circuit consisted of 4 NMOS of load resistance, which convert the output impedenceby tuning on or off. The result show the gain change by NMOS operated swich. The simulation result is that Gain is 14.07dB-16.79dB and NF(Noise Figure) is 1.06dB-1.09dB.