• 한국정보통신학회논문지
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• 제8권8호
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• pp.1719-1724
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• 2004

본 논문에서는 차세대 RF 전력 소자로 기대하고 있는 LDMOST의 BV(Breakdown; 항복전압) 특성을 향상시키는 새로운 구조를 제안하였다. 제안한 구조는 외부 전계 링이라 하며 드리프트 영역 둘레에 3차원적인 구조로 형성된다. 외부 전계 링은 드리프트 영역에서 전계를 완화시키는 역할을 함으로써 BV 특성을 향상시키는 효과를 얻을 수 있다. 3차원 TCAD 시뮬레이션 결과, 외부 전계 링의 접합깊이와 도핑 농도의 증가에 따라 LDMOST의 BV가 증가함을 확인할 수 있었다. 따라서 기존의 p+ sinker 공정을 사용하여 외부 전계 링 구조를 추가한다면 LDMOST의 BV 특성을 크게 향상 시킬 수 있다.

• 전기전자학회논문지
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• 제24권2호
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• pp.592-597
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• 2020

SiC는 Si에 비해서 Breakdown field가 10배 높고, Energy gap이 3배 높기 때문에 높은 Breakdown voltage를 갖는 우수한 전력 MOSFET을 제작할 수 있다. 하지만 낮은 Mobility로 인한 높은 On저항을 갖기 때문에 이를 낮추기 위해서 Trench MOSFET이 제안되었지만 동시에 BV가 감소한다는 문제점을 갖는다. 본 논문에서는 1200V급 Trench MOSFET 설계를 목적으로 하며, 이를 해결하기 위해서 BV와 Ron에 대한 중요한 변수인 Epi 깊이, Trench 깊이, Trench 깊이에서 Epi 깊이까지의 거리에 대한 Split을 진행하여 최대 전계, BV, Ron의 신뢰성 특성을 비교 분석하였다. Epi 깊이가 증가할수록, Trench 깊이가 감소할수록, Trench 깊이에서 Epi 깊이가 감소할수록 최대 전계 감소, BV 증가, Ron 증가를 확인하였다. 모든 결과는 Sentaurus TCAD를 통해 Simulation 되었다.

• 전기전자학회논문지
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• 제24권1호
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• pp.284-292
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• 2020

SiC 기반 소자는 silicon 소자 대비 1200V 이상의 고전압 환경에서 우수하게 동작하며 특히 매우 높은 온도에서 안정적인 특성을 보여준다. 따라서 최근 1700V급 UMOSFET이 전기 자동차, 항공기 등의 전력시스템의 사용을 목표로 활발하게 연구개발 되고 있다. 본 논문에서는 최근 연구되고 있는 세 종류의 1700급 UMOSFET-Conventional UMOSFET (C-UMOSFET), Source Trench UMOSFET (ST-UMOSFET), Local Floating Superjunction UMOSFET (LFS-UMOSFET)-에 대해 온도 변화(300K-600K)에 따른 전력소자에서 중요한 변수 (breakdown voltage(BV), on-resistance(R_on), threshold voltage(v_th), transconductance(g_m))의 신뢰성 특성을 비교 분석하였다. 세 소자 모두 온도 증가에 따른 BV 증가, R_on 증가, v_th 감소, g_m 감소를 확인하였다. 그러나 세 소자의 구조 차이에 따라 BV, R_on v_th, g_m 변화에 차이가 있어 그 정도 및 원인에 대해 비교 분석하였다. 모든 결과는 sentaurus TCAD을 통해 simulation 되었다.

• ETRI Journal
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• 제36권5호
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• pp.829-834
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• 2014

In this paper, a lateral power metal-oxide-semiconductor field-effect transistor with ultra-low specific on-resistance is proposed to be applied to a high-voltage (up to 200 V) integrated chip. The proposed structure has two characteristics. Firstly, a high level of drift doping concentration can be kept because a tilt-implanted p-drift layer assists in the full depletion of the n-drift region. Secondly, charge imbalance is avoided by an extended trench gate, which suppresses the trench corner effect occurring in the n-drift region and helps achieve a high breakdown voltage (BV). Compared to a conventional trench gate, the simulation result shows a 37.5% decrease in $R_{on.sp}$ and a 16% improvement in BV.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기물성,응용부문
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• pp.156-158
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• 2002

Reduction of on-resistance($R_{on}$) in high voltage devices is of critical importance for the power consumption of the device. $R_{on}$ decreases with increase of the doping concentration of the drift region. However, breakdown voltage(BV) decreaes also with increase of doping concentration. In this report, a multi-resurf LDMOS[1] strcuture is proposed to reduce the $R_{on}$ which allows no degradation in BV. The on-and off-state characteristics of the proposed structure are simulated using the two-dimensional devices simulator ATLAS and compared with those from the conventional structure.

• 전기전자학회논문지
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• 제22권3호
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• pp.565-569
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• 2018

For the conventional power MOSFET (metal-oxide semiconductor field-effect transistor) device structure, there exists a tradeoff relationship between specific on-state resistance (Ron,sp) and breakdown voltage (BV). In order to overcome this tradeoff, a super-junction (SJ) trench MOSFET (TMOSFET) structure with uniform or non-uniform doping concentration, which decreases linearly in the vertical direction from the N drift region at the bottom to the channel at the top, for an optimal design is suggested in this paper. The on-state resistance of $0.96m{\Omega}-cm2$ at the SJ TMOSFET is much less than that at the conventional power MOSFET under the same breakdown voltage of 100V. A design methodology for the edge termination is proposed to achieve the same breakdown voltage and on-state resistance as the main body of the super-junction TMOSFET by using of the SILVACO TCAD 2D device simulator, Atlas.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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• pp.170-173
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• 2003

In this paper, we proposed a new bulk LDMOS structure which can be used for RF application, and its fabrication steps were introduced. The simulated devices consist of three types: Bulk device, SLB(SOI Like Bulk), and SOI device. As a result of process and device simulation, we showed electrical characteristics, such as threshold voltage, subthreshold slope, DIBL(Drain Induced Barrier Lowering), off-state current, and breakdown voltage. In this simulation study, the lattice temperature model was adopted to see the device characteristics with lattice temperature during the operation. SLB device structure showed the best breakdown characteristics among the other structures. The breakdown voltage of SLB structure is about 9V, that of bulk is 7V, and that of SOI is 8V.

• 한국전기전자재료학회논문지
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• 제25권9호
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• pp.671-676
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• 2012

In this paper, TCAD assessment of 30-V class n-channel EDMOS (extended drain metal-oxide-semiconductor) transistors with DWFG (dual work function gate) structure are described. Gate of the DWFG EDMOS transistor is composed of both p- and n-type doped region on source and drain side. Additionally, lengths of p- and n-type doped gate region are varied while keeping physical channel length. Two-dimensional device structures are generated trough TSUPREM-4 and their electrical characteristics are investigated with MEDICI. The DWFG EDMOS transistor shows improved electrical characteristics than conventional device - i.e. higher transconductance ($g_m$), better drain output current ($I_{ON}$), reduced specific on-resistances ($R_{ON}$) and higher breakdown characteristics ($BV_{DSS}$).

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.66-77
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• 2010

Improvement in breakdown voltage ($BV_{ds}$) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length ($L_g$), but due to lithographic limitation, shortening $L_g$ below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the $BV_{ds}$ of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in $BV_{ds}$ can be obtained by applying field plates, especially at the drain side. The important parameters affecting $BV_{ds}$ and cut-off frequency ($f_T$) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, $\Gamma$-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권6호
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• pp.257-260
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• 2003

We have proposed the junction termination structure of IGBT (Insulated Gate Bipolar Transistor) by employing trench and FLR (Field Limiting Ring), which decrease the junction termination area at the same breakdown voltage. Our proposed junction termination structure, trench FLR is verified by numerical simulator MEDICI. In 600V rated device, the junction termination area is decreased 20% compared with that of the conventional FLR structure. The breakdown voltage of trench FLR with 4 trenches is 768 V, 99 % of ideal parallel-plane junction(1-D) $BV_ceo$.