• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.8
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• pp.1719-1724
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• 2004

In this paper, we have proposed a new structure of LDMOST, which has been expected as a next generation RF power device, to improve the BV(Breakdown Voltage) characteristics. The proposed structure, named external field ring, is formed around a drift region by the three dimensional structure. The external field ring relieves the electric field in the drift region and improves the BV characteristics. By the three dimensional TCAD simulations, it was found that the BV of LDMOST was increased by the increase of the junction depth and doping concentration of the external field ring. Therefore, the BV characteristics of the LDMOST can be remarkably improved by addition of external field ring using an existing p+ sinker process.

• Journal of IKEEE
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• v.24 no.2
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• pp.592-597
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• 2020

Since SiC has 10 times higher breakdown field and 3 times higher energy gap than Si, it is possible to manufacture an excellent power MOSFET with a high breakdown voltage. However, since it has a high on-resistance due to low mobility, a Trench MOSFET has been proposed to lower it, but at the same time, it has a problem that BV decreases. The purpose of this paper is to design a 1200V trench MOSFET, and to solve this, split Epi depth, Trench depth, and Trench depth to Epi depth, which are important variables for BV and Ron, to achieve maximum electric field, BV, Ron's reliability characteristics were compared and analyzed. As the epi depth increased, the trench depth decreased, and the epi depth decreased at the trench depth, the maximum electric field decrease, BV increase, and Ron increase were confirmed. All results were simulated by sentaurus TCAD.

• Journal of IKEEE
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• v.24 no.1
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• pp.284-292
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• 2020

SiC-based devices perform well in high-voltage environments of more than 1200V compared to silicon devices, and are particularly stable at very high temperatures. Therefore, 1700V UMOSFET has been actively researched and developed for the use of electric power systems such as electric vehicles and aircrafts. In this paper, we analysed thermal variations of critical variables (breakdown voltage (BV), on-resistance (R_on), threshold voltage (v_th), and transconductance (g_m)) for the three type 1700V UMOSFETs-Conventional UMOSFET (C-UMOSFET), Source Trench UMOSFET (ST-UMOSFET), and Local Floating Superjunction UMOSFET (LFS-UMOSFET). All three devices showed BV increase, R_on increase, v_th decrease, and g_m decrease with increasing temperature. However, there are differences in BV, R_on, v_th, g_m according to the structural differences of the three devices, and the degree and cause of the analysis were compared. All results were simulated using sentaurus TCAD.

• ETRI Journal
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• v.36 no.5
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• pp.829-834
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• 2014

In this paper, a lateral power metal-oxide-semiconductor field-effect transistor with ultra-low specific on-resistance is proposed to be applied to a high-voltage (up to 200 V) integrated chip. The proposed structure has two characteristics. Firstly, a high level of drift doping concentration can be kept because a tilt-implanted p-drift layer assists in the full depletion of the n-drift region. Secondly, charge imbalance is avoided by an extended trench gate, which suppresses the trench corner effect occurring in the n-drift region and helps achieve a high breakdown voltage (BV). Compared to a conventional trench gate, the simulation result shows a 37.5% decrease in $R_{on.sp}$ and a 16% improvement in BV.

• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.156-158
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• 2002

Reduction of on-resistance($R_{on}$) in high voltage devices is of critical importance for the power consumption of the device. $R_{on}$ decreases with increase of the doping concentration of the drift region. However, breakdown voltage(BV) decreaes also with increase of doping concentration. In this report, a multi-resurf LDMOS[1] strcuture is proposed to reduce the $R_{on}$ which allows no degradation in BV. The on-and off-state characteristics of the proposed structure are simulated using the two-dimensional devices simulator ATLAS and compared with those from the conventional structure.

• Journal of IKEEE
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• v.22 no.3
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• pp.565-569
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• 2018

For the conventional power MOSFET (metal-oxide semiconductor field-effect transistor) device structure, there exists a tradeoff relationship between specific on-state resistance (Ron,sp) and breakdown voltage (BV). In order to overcome this tradeoff, a super-junction (SJ) trench MOSFET (TMOSFET) structure with uniform or non-uniform doping concentration, which decreases linearly in the vertical direction from the N drift region at the bottom to the channel at the top, for an optimal design is suggested in this paper. The on-state resistance of $0.96m{\Omega}-cm2$ at the SJ TMOSFET is much less than that at the conventional power MOSFET under the same breakdown voltage of 100V. A design methodology for the edge termination is proposed to achieve the same breakdown voltage and on-state resistance as the main body of the super-junction TMOSFET by using of the SILVACO TCAD 2D device simulator, Atlas.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.170-173
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• 2003

In this paper, we proposed a new bulk LDMOS structure which can be used for RF application, and its fabrication steps were introduced. The simulated devices consist of three types: Bulk device, SLB(SOI Like Bulk), and SOI device. As a result of process and device simulation, we showed electrical characteristics, such as threshold voltage, subthreshold slope, DIBL(Drain Induced Barrier Lowering), off-state current, and breakdown voltage. In this simulation study, the lattice temperature model was adopted to see the device characteristics with lattice temperature during the operation. SLB device structure showed the best breakdown characteristics among the other structures. The breakdown voltage of SLB structure is about 9V, that of bulk is 7V, and that of SOI is 8V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.9
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• pp.671-676
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• 2012

In this paper, TCAD assessment of 30-V class n-channel EDMOS (extended drain metal-oxide-semiconductor) transistors with DWFG (dual work function gate) structure are described. Gate of the DWFG EDMOS transistor is composed of both p- and n-type doped region on source and drain side. Additionally, lengths of p- and n-type doped gate region are varied while keeping physical channel length. Two-dimensional device structures are generated trough TSUPREM-4 and their electrical characteristics are investigated with MEDICI. The DWFG EDMOS transistor shows improved electrical characteristics than conventional device - i.e. higher transconductance ($g_m$), better drain output current ($I_{ON}$), reduced specific on-resistances ($R_{ON}$) and higher breakdown characteristics ($BV_{DSS}$).

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.66-77
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• 2010

Improvement in breakdown voltage ($BV_{ds}$) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length ($L_g$), but due to lithographic limitation, shortening $L_g$ below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the $BV_{ds}$ of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in $BV_{ds}$ can be obtained by applying field plates, especially at the drain side. The important parameters affecting $BV_{ds}$ and cut-off frequency ($f_T$) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, $\Gamma$-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.6
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• pp.257-260
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• 2003

We have proposed the junction termination structure of IGBT (Insulated Gate Bipolar Transistor) by employing trench and FLR (Field Limiting Ring), which decrease the junction termination area at the same breakdown voltage. Our proposed junction termination structure, trench FLR is verified by numerical simulator MEDICI. In 600V rated device, the junction termination area is decreased 20% compared with that of the conventional FLR structure. The breakdown voltage of trench FLR with 4 trenches is 768 V, 99 % of ideal parallel-plane junction(1-D) $BV_ceo$.