• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.155-162
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• 1999

A bare chip packaging technology by an encapsulated flip chip bonding on a build-up printed circuit board has emerged in 1991. Since then, it enabled a high density and low cost semiconductor packaging such as a direct chip bonding on mother board and high density surface mount components, such as BGA and CSP. This technology can respond to various requirements from applications and is considered to take over a main role of semiconductor packaging in the next decade.

• 한국재료학회지
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• 제15권3호
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• pp.183-188
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• 2005

It was studied in this article how the flexural strength of bare silicon chips is influenced by adopting dual wafer back-lapping process. The experimental results showed that an additional finishing process after the conventional grinding process improves the flexural strength of bare chips by more than 2-fold. In particular, this work showed that the proper removal of the grinding marks$(Ra=0.1\;{\mu}m)$existing on the wafer back-surface resulting from the grinding process significantly contiributes to the enhancement of chip strength.

• 한국공작기계학회논문집
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• 제17권1호
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• pp.120-125
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• 2008

A flip-chip bonding system using DPSS(Diode Pumped Solid State) Nd:YAG laser(wavelength : 1064nm) which shows a good quality in fine pitch bonding is developed. This laser bonder can transfer beam energy to the solder directly and melt it without any physical contact by scanning a bare chip. By using a laser source to heat up the solder balls directly, it can reduce heat loss and any defects such as bridge with adjacent solder, overheating problems, and chip breakage. Comparing to conventional flip-chip bonders, the bonding time can be shortened drastically. This laser precision micro bonder can be applied to flip-chip bonding with many advantage in comparison with conventional ones.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2005년도 춘계 학술대회
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• pp.79-83
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• 2005

IT 기술, 반도체 산업 등의 급격한 발전에 힘입어 최근의 첨단 전자, 통신제품은 초경량 초소형화와 동시에 고기능 복합화의 발전 추세를 보이고 있다. 이런 추세에 발맞추어 전자제품, 통신제품의 핵심적인 부품인 IC chip도 소형화되고 있다. IC chip 패키징 기술의 하나인 Filp Chip Package는 Module Substrate 위에 Chip Surface를 Bumping 시킴으로서 최단의 접속길이와 저열저항, 저유전율의 특성도 가지면서 초소형에 높은 수율의 저 원가생산성을 갖는 첨단의 패키징 기술이다. 이런 패키징 기술은 수요증가와 더불어 폭발적으로 늘어나고 있으나 까다로운 공정기술에 의해 아직 여러 회사에서 장비가 출시되고 있지 못한 상태이다. 이에 본 연구에서는 최근 수요가 증가하는 LCD Driver IC용 COF 장비를 위한 Flip chip Bonding 장비 및 시스템을 설계, 제작하였다.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회A
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• pp.1673-1678
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• 2007

The use of flip-chip type electronic package offers numerous advantages such as reduced thickness, improved environmental compatibility, and downed cost. Despite numerous benefits, flip-chip type packages bare several reliability problems. The most critical issue among them is their electrical performance deterioration upon consecutive thermal cycles attributed to gradual delamination growth through chip and adhesive film interface induced by CTE mismatch driven shear and peel stresses. The electronic package in use is heated continuously by itself. When the crack at a weak site of the electronic package occurs, thermal deformationon the chip side is changed. Therefore, we can measure these micro deformations by using Moire interferometry and find out the crack length.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.127-154
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• 1999

Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

• 한국ITS학회 논문지
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• 제2권2호
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• pp.65-72
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• 2003

본 연구를 통하여 MMC(Microwave Micro Cell)를 위한 무선 중계 시스템과 ITS용 무선장비등에 사용 될 수있는 6단의 하이브리드 전력증폭기를 설계 및 제작하였다. 전력 증폭기 각단의 능동소자는 bare chip 형태의 Hetero-junction Power FET를 이용하였으며, $\varepsilon_{r}$=9.9, 15-mil 두께의 알루미나기판을 사용하여 제작하였다. 측정 결과 시스템의 순방향 주파수인 17.6GHz - 17.gGEU에서 33.2~36.5dB의 소신호 이득과 33.0$\~$34.0dBm까지의 출력전력을 얻었고, 역방향 주파수인 19.0GHt$\~$19.2GHz에서 36.0$\~$37.0dB의 소신호 이득을 출력전력은 33.0$\~$34.5dBm을 얻었다.

• 전자공학회논문지A
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• 제31A권3호
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• pp.28-39
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• 1994

We experimented on memory multichip modules to increase the packing density of memory devices and to improve their electrical characteristics. A 128K$\times$8bit SRAM module was made of four 32K$\times$8bit SRAM memory chips. The memory multichip module was constructed on a low-cost double sided PCB(printed circuit boared) substrate. In the process of fabricating a multichip module. we focused on the improvement of its electrical characteristics. volume, and weight by employing bare memory chips. The characteristics of the bare chip module was compared with that of the module with four packaged chips. We conducted circuit routing with a PCAD program, and found the followings: the routed area for the module with bare memory chips reduced to a quarter of that area for module with packaged memory chips. 1/8 in volume, 1/5 in weight. Signal transmission delay times calculated by using transmission line model was reduced from 0.8 nsec to 0.4 nsec only on the module board, but the coupling coefficinet was not changed. Thus, we realized that the electrical characteristics of multichip packages on PCB board be improved greatly when using bare memory chips.

• 전자공학회논문지
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• 제50권4호
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• pp.203-211
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• 2013

태그 안테나를 설계할 때에는 태그 칩이 패드(pad)에 마운트(mount)된 상태에서 구한 칩 임피던스(chip impedance)와 읽기 전력감도(read power sensitivity) 값이 필요하다. 하지만 칩 임피던스 값은 태그 설계와 제조공정에 따라 그 값이 달라지기 때문에 칩 제조회사들이 이 자료를 제공하지 못하고, 단지 참고할 수 있는 근사값을 만을 제고하고 있다. 본 연구는 간단한 보조기구들과 RF 측정장비들을 가지고 마운트된 칩의 임피던스와 읽기 전력감도를 산출할 수 있는 방법을 제시한다. 본 연구는 마운틴된 칩의 단자에서 직접 측정하는 것이 불가능하기 때문에 보조 픽스쳐(fixture)들이 사용되었으며, 보조 픽스쳐에서 발생되는 전기력 특성들은 등가회로 모델과 디임베드(de-embed) 기법을 사용하여 제거함으로써 칩 임피던스와 읽기 전력감도 값을 산출하였다. 값을 알고 있는 커패시터와 저항 칩을 가지고 제안된 디임베드 방법의 타당성과 정확도를 검증하였으며, 상업용 태그 칩을 대상으로 한 심험에서도 제안된 방법의 타당성을 재확인 할 수 있다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 2nd Korea-Japan Advanceed Semiconductor Packaging Technology Seminar
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• pp.39-45
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• 2000

A small camera module fabricated by including bare chip bonding methods is utilized to realize advanced mobile devices. One of the driving forces is the TOG (Tape On Glass) bonding method which reduces the packaging size of the image sensor clip. The TOG module is a new thinner and smaller image sensor module, using flip chip interconnection method with the ACP (Anisotropic Conductive Paste). The TOG production process was established by determining the optimum bonding conditions for both optical glass bonding and image sensor clip bonding lo the flexible PCB. The bonding conditions, including sufficient bonding margins, were studied. Another bonding method is the flip chip bonding method for DSP (Digital Signal Processor) chip. A new AC\ulcorner was developed to enable the short resin curing time of 10 sec. The bonding mechanism of the resin curing method was evaluated using FEM analysis. By using these flip chip bonding techniques, small camera module was realized.