• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.1-9
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• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• ETRI Journal
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• v.32 no.1
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• pp.154-156
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• 2010

Oscillation-based testing of analog-to-digital converters represents a viable option for low-cost built-in self-testing in mixed-signal design. While numerous papers have addressed implementation issues, little attention has been paid to the measurement accuracy. In this letter, we highlight an inherent measurement uncertainty which has to be considered when deriving the parameters from the oscillation frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1619-1626
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• 2021

Unlike traditional delta-sigma analog-to-digital converters, incremental analog-to-digital converters enable 1:1 mapping of input and output through a reset operation, which can be used very easily for multiplexing. Incremental analog-to-digital converters also allow for simpler digital filter designs compared to traditional delta-sigma converters. Therefore, starting with analysis in the time domain of the delayed integrator and non-delayed integrator, which are the basic blocks of analog-to-digital converter design, the design equations of a second-order input feed-forward, extended counting, 2+1 MASH (Multi-stAge-noise-SHaping), 2+2 MASH incremental analog-to-digital converter are derived in this paper. This allows not only prediction of the performance of the incremental analog-to-digital converter before design, but also the design of a digital filter suitable for each analog-to-digital converter. In addition, extended counting and MASH design techniques were proposed to improve the accuracy of analog-to-digital converters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.22-28
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• 2008

This paper designed a efficient 8-bit CMOS analog-to-digital converter(ADC) for an SOC(System On Chip) application. The architecture consists of two modified 4-bit full-flash ADCs, it has been designed using a more efficient architecture. This is to predict roughly the range in which input signal residers and can be placed in the proximity of input signal based on initial prediction. The prediction of input signal is made available by introducing a voltage estimator. For 4-bit resolution, the modified full-flash ADC need only 6 comparators. So a 8-bit ADC require only 12 comparators and 32 resistors. The speed of this ADC is almost similar to conventional full-flash ADC, but the die area consumption is much less due to reduce numbers of comparators and registors. This architecture uses even fewer comparator than half-flash ADC. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.

• Journal of Power Electronics
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• v.17 no.3
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• pp.686-694
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• 2017

Due to the wide use of electronic products, digitally controlled DC-DC converters are attracting more and more attention in recent years. However, digital control strategies may introduce undesirable Limit Cycle Oscillation (LCO) due to quantization effects in the Analog-to-Digital Converter (ADC) and Digital Pulse Width Modulator (DPWM). This results in decreases in the quality of the output voltage and the efficiency of the system. Meanwhile, even if the resolution of the DPWM is finer than that of the ADC, LCO may still exist due to improper parameters of the digital compensator. In order to discover how LCO is generated, the state space averaging model is applied to derive equilibrium equations of a digital PID controlled DC-DC converter in this paper. Furthermore, the influences of the parameters of the digital PID compensator, and the resolutions of the ADC and DPWM on LCO are studied in detail. The amplitude together with the period of LCO as well as the corresponding PID parameters are obtained. Finally, MATLAB/Simulink simulations and FPGA verifications are carried out and no-LCO conditions are obtained.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.20-27
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• 1997

In this paper, a multiplying digital-to-analog converter (MDAC) circuit for low-power high-resolution CMOS algorithmic A/D converters (ADC's) is proposed. The proposed MDAC is designed to operte properly at a supply at a supply voltge between 3 V and 5 V and employs an analog0domain power reduction technique based on a bias switching circuit so that the total power consumption can be optimized. As metal-to-metal capacitors are implemented as frequency compensation capacitors, opamps' performance can be varied by imperfect process control. The MDAC minimizes the effects by the circuit performance variations with on-chip tuning circuits. The proposed low-power MDAC is implementd as a sub-block of a 10-bit 200kHz algorithmic ADC using a 0.6 um single-poly double-metal n-well CMOS technology. With the power-reduction technique enabled, the power consumption of the experimental ADC is reduced from 11mW to 7mW at a 3.3V supply voltage and the power reduction ratio of 36% is achieved.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.19-29
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• 2003

This paper proposes a CMOS readout circuit for uncooled micro-bolometer arrays adopting a four-point step calibration technique. The proposed readout circuit employing an 11b analog-to-digital converter (ADC), a 7b digital-to-analog converter (DAC), and an automatic gain control circuit (AGC) extracts minute infrared (IR) signals from the large output signals of uncooled micro-bolometer arrays including DC bias currents, inter-pixel process variations, and self-heating effects. Die area and Power consumption of the ADC are minimized with merged-capacitor switching (MCS) technique adopted. The current mirror with high linearity is proposed at the output stage of the DAC to calibrate inter-pixel process variations and self-heating effects. The prototype is fabricated on a double-poly double-metal 1.2 um CMOS process and the measured power consumption is 110 ㎽ from a 4.5 V supply. The measured differential nonlinearity (DNL) and integrat nonlinearity (INL) of the 11b ADC show $\pm$0.9 LSB and $\pm$1.8 LSB, while the DNL and INL of the 7b DAC show $\pm$0.1 LSB and $\pm$0.1 LSB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.61-70
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• 2009

A 10b 30MS/s pipelined ADC operating under 1V power supply is presented. It utilizes a switched-RC based input sampling circuit and a resistive loop to reset the feedback capacitor in the multiplying digital-to-analog converter (MDAC) for the low-voltage operation. Cascaded switched-RC branches are used to achieve accurate grain of the MDAC for the first stage and separate switched-RC circuits are used in the sub-ADC to suppress the switching noise coupling to the MDAC input The measured differential and integral non-linearities of the prototype ADC fabricated in a 0.13${\mu}m$, CMOS process are less than 0.54LSB and 1.75LSB, respectively. The prototype ADC achieves 54.1dB SNDR and 70.4dB SFDR with 1V supply and 30MHz sampling frequency while consuming 17mW power.

• Journal of the Korean Magnetics Society
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• v.22 no.2
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• pp.45-48
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• 2012

Feed-back type 3-axis flux-gate magnetometer using Co-based amorphous ribbon (Metglass$^{(R)}$2714A) was constructed in this work. Measuring range of magnetic field and frequency were ${\pm}100\;{\mu}T$ and dc~10 Hz respectively. For the interface to computer, microcontroller and 24 bit ADC (Analog to Digital Converter) were employed and resolution of digital output was 0.1 nT. Magnetometer noise of analog output was 5 pT/$\sqrt{Hz}$ at 1 Hz. Digital output of the magnetometer showed linearity of $1{\times}10^{-4}$ and the offset drift was smaller than 0.2 nT during 1 h.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.549-550
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• 2008

This paper proposed and designed the modified flash analog-to-digital converter(ADC). The speed of new architecture is similar to conventional flash ADC but the die area consumption is much less due to reduce numbers of comparators. The circuits which are implemented in this paper is simulated with LT SPICE and layout with Electric tools of computer.