1 |
Michael Choi and Asad A. Abidi, "A 6b 1.3Gsample/s A/D Converter in 0.35- CMOS," IEEE J. Solid-State Circuits, Vol.36, No.12, pp.1847-1858, Dec., 2001.
DOI
ScienceOn
|
2 |
Govert Geelen and Edward Paulus, "An 8b 600 MS/s 200 mW CMOS folding A/D Converter Using an Amplifier Preset Technique," in ISSCC Dig. Tech. Papers, pp.254-256, Feb., 2004.
|
3 |
Hamid Movahedian, Mehrdad Sharif Bakhtiar, "A New Offset Cancellation Technique for Folding ADC," in Proc. IEEE ISCAS, Vol.1, pp.200-203, May., 2005.
|
4 |
Alireza Razzaghi, et al., "A Single-Channel 10b 1GS/s ADC with 1-cycle Latency using Pipelined Cascaded Folding," in Proc. BCTM, pp.265-268, Oct., 2008.
|
5 |
Ashutosh Verma and Behzad Razavi, "A 10-Bit 500-MS/s 55-mW CMOS ADC," IEEE J. Solid-State Circuits, Vol.44, No.11, pp.3039-3050, Nov., 2009.
DOI
ScienceOn
|
6 |
Robert C. Taft, et al., "A 1.8V 1.0GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency," IEEE J. Solid-State Circuits, Vol.44, No.12, pp.3294-3304, Dec., 2009.
DOI
ScienceOn
|
7 |
Simon M. Louwsma, et al., "A 1.35GS/s, 10b, 175 mW Time-Interleaved AD Converter in CMOS," IEEE J. Solid-State Circuits, Vol.43, No.4, pp.778-786, Apr., 2008.
DOI
ScienceOn
|
8 |
Robert C. Taft, et al., "A 1.8-V 1.6-GSample/s 8-b Self-Calibrating folding ADC With 7.26 ENOB at Nyquist Frequency," IEEE J. Solid-State Circuits, Vol.39, No.12, pp.2107-2115, Dec., 2004.
DOI
ScienceOn
|
9 |
Hee-Cheol Choi, et al., "A Rail-to-Rail Input 12b 2 MS/s 0.18um CMOS Cyclic ADC for Touch Screen Applications," Journal of Semiconductor Technology and Science, Vol.9, No.3, pp.160-165, Sep., 2009.
DOI
ScienceOn
|
10 |
Jinup Lim, et al., "A 9-bit ADC with a Wide-Range Sample-and-Hold Amplifier," Journal of Semiconductor Technology and Science, Vol.4, No.4, pp.280-285, Dec., 2004.
과학기술학회마을
|
11 |
Ivan Bogue and Michael P. Flynn, "A 57dB SFDR Digitally Calibrated 500 MS/s folding ADC in 0.18 digital CMOS," in Proc. IEEE CICC, pp.337-340. Sep., 2007.
|
12 |
Huseyin Dinc and Phillip E. Allen, "A 1.2 GSample/s Double-Switching CMOS THA With-62 dB THD," IEEE J. Solid-State Circuits, Vol.44, No.3, pp.848-861, Mar., 2009.
DOI
ScienceOn
|
13 |
Andrew M. Abo and Paul R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter," IEEE J. Solid-State Circuits, Vol.34, No.5, pp.599-606, May., 1999.
DOI
ScienceOn
|