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Design of Efficient 8bit CMOS AD Converter for SOC Application  

Kwon, Seung-Tag (Department of Computer and Information communication, Seonam University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.12, 2008 , pp. 22-28 More about this Journal
Abstract
This paper designed a efficient 8-bit CMOS analog-to-digital converter(ADC) for an SOC(System On Chip) application. The architecture consists of two modified 4-bit full-flash ADCs, it has been designed using a more efficient architecture. This is to predict roughly the range in which input signal residers and can be placed in the proximity of input signal based on initial prediction. The prediction of input signal is made available by introducing a voltage estimator. For 4-bit resolution, the modified full-flash ADC need only 6 comparators. So a 8-bit ADC require only 12 comparators and 32 resistors. The speed of this ADC is almost similar to conventional full-flash ADC, but the die area consumption is much less due to reduce numbers of comparators and registors. This architecture uses even fewer comparator than half-flash ADC. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.
Keywords
Flash ADC; Voltage estimator; SOC; Thermometer code; Comparator;
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