• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.83-92
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• 2004

In this thesis, a modified interpolation-2 6-bit 70MHz ADC is proposed minimizing chip area and power consumption, which includes an error correction circuit. The conventional flash ADC without interpolation comparators suffers from large chip area and more power consumption due to 2n resistors and 2n-1 comparators. Although the flash ADC with interpolation-4 comparators has small area, SNR, INL and DNL are degraded by comparison with the interpolation -2 comparator. We fabricated the proposed 6-bit ADC with interpolation-2 comparators using 0.18${\mu}{\textrm}{m}$ CMOS process. The ADC is composed of 32-resistors, 31 comparators, amplifiers, latches, error correction circuit, thermometer code detector and encoder As the results, power consumption is reduced to 40mW at 3.3V which is saving about 50% than a flash ADC without interpolation comparators, and area is reduced by 20%. SNR is increased by 75% in comparison with that of a flash ADC with interpolation-4 comparators.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.143-146
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• 2011

A 50-MS/s 10-bit pipelined ADC with 1.2Vpp differential input range is proposed in this paper. The designed pipelined ADC consists of eight stage of 1.5bit/stage, one stage of 2bit/stage, digital error correction block, bias & reference driver, and clock generator. 1.5bit/stage is consists of sub-ADC, DAC and gain stage, Specially, a sample-and hold amplifier (SHA) is removed in the designed pipelined ADC to reduce the hardware and power consumption. Also, the proposed bootstrapped switch improves the Linearity of the input analog switch and the dynamic performance of the total ADC. The reference voltage was driven by using the on-chip reference driver without external reference. The proposed pipelined ADC was designed by using a 0.18um 1-poly 5-metal CMOS process with 1.8V supply. The total area including the power decoupling capacitor and power consumption are $0.95mm^2$ and 60mW, respectively. Also, the simulation result shows the ENOB of 9.3-bit at the Nyquist sampling rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.1-7
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• 2012

A 9b MS/s CMOS cyclic folding A/D converter (ADC) for intelligent battery sensor and battery management systems is proposed. The proposed ADC structure is based on a cyclic architecture to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding-interpolating structure. The prototype ADC implemented with a 0.35um 2P4M n-well CMOS process shows a measured INL and DNL of maximum 1.5LSB and 1.0LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 48dB and 60dB, respectively, and the power consumption is about 110mW at 2MS/s and 3.3V. The occupied active die area is $10mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.8-8
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• 2004

본 논문에서는 새로운 interpolation-2 방식의 비교기 구조를 제안하여 칩 면적과 전력 소모를 줄이며 오류정정 회로를 내장하는 6-비트 70㎒ ADC를 설계하였다. Interpolation 비교기를 적용하지 않은 flash ADC의 경우 2n개의 저항과 2n -1개의 비교기가 사용되며 이는 저항의 수와 비교기의 수에 비례하여 많은 전력과 큰 면적을 필요로 하고 있다. 또한, interpolation-4 비교기를 적용한 flash ADC는 면적은 작으나 단조도, SNR, INL, DNL 특성이 떨어진다는 단점이 있었다. 본 논문에서 설계한 interpolation-2 방식의 ADC는 저항, 비교기, 앰프, 래치, 오류정정 회로, 온도계코드 디텍터와 인코더로 구성되며, 32개의 저항과 31개의 비교기를 사용하였다. 제안된 회로는 0.18㎛ CMOS 공정으로 제작되어 3.3V에서 40mW의 전력소모로 interpolation 비교기를 적용하지 않은 flash ADC에 비해 50% 개선되었으며, 칩 면적도 20% 감소되었다. 또한 노이즈에 강한 오류정정 회로가 사용되어 interpolation-4 비교기를 적용한 flash ADC 에 비해 SNR이 75% 개선된 결과를 얻었다.

• Journal of Chest Surgery
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• v.37 no.12
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• pp.967-977
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• 2004

Background: DNA methylation is one of the important gene expression mechanisms of the cell. When cytosine of CpG dinucleotide in promotor is hypomethylated, expression of some genes that is controlled by this promoter is altered. In this study, the author investigated the effect of DNA demethylating agent, 5-aza-2'-deoxycytidine (ADC), on the expressions of cancer antigen genes, MHC and B7 in 4 lung cancer cell lines, NCIH1703, NCIH522, MRC-5, and A549. Material and Method: After treatment of cell lines, NCIH1703, NCIH522, MRC-5 and A549 with ADC (1 uM) for 48 hours, RT-PCR was performed by using the primers of MAGE, GAGE, NY-ESO-1, PSMA, CEA, and SCC antigen gene. In order to find the optimal ADC treatment condition for induction of cancer antigen, we studied the effect of ADC treatment time and dose on the cancer antigen gene expression. To know the effect of ADC on the expression of MHC or B7 and cell growth, cells were treated with 1 uM of ADC for 72 hours for FACS analysis or cells were treated with 0.2, 1 or 5 uM of ADC for 96 hours for cell counting. Result: After treatment of ADC (1 uM) for 48 hours, the expressions of MAGE, GAGE, NY-ESO-1, and PSMA genes increased in some cell lines. Among 6 MAGE isotypes tested, and gene expression of MAGE-1, -2, -3, -4 and -6 could be induced by ADC treatment. However, CEA gene expression did not change and SCC gene expression was decreased by ADC treatment. Gene expression was generally induced 24 - 28 hours after ADC treatment and expression of MAGE, GAGE, and NY-ESO-1 was maintained at least 14 days after ADC ADC teatment, and expression of MAGE, GAGE, and NY-ESO-1 was maintained at least 14 days after ADC teatment in ADC-Free medium. Most gene expression could be induced at 0.2 uM of ADC, but gene expression increased dependently on ADC treatment dose. The expression of MHC and B7 was not increased by ADC treatment in all four cell lines, and the growth rate of 4 cell lines decreased significantly with the increase of ADC concentrations. Conclusion: Treatment of lung cancer cell lines with ADC increases the gene expression MAGE, GAGE and NY-ESO-1 that are capable of induction of cytotoxic T lymphocyte response. We suggest that treatment with 1 uM of ADC for 48 hours and then culturing in ADC-free medium is optimal condition for induction of cancer antigen. However, ADC has no effect on MHC and B7 induction, additional modification for increase of expression of MHC, B7 and cytokine will be needed for production of efficient cancer cell vaccine.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.800-807
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• 2006

To enhance the conversion speed more fast, we separate the determination process of MSB and LSB with the two independent ADC circuits of the Incremental Sigma Delta ADC. After the 1st Incremental Sigma Delta ADC conversion finished, the 2nd Incremental Sigma Delta ADC conversion start while the 1st Incremental Sigma Delta ADC work on the next input. By determining the MSB and the LSB independently, the ADC conversion speed is improved by two times better than the conventional Extended Counting Incremental Sigma Delta ADC. In processing the 2nd Incremental Sigma Delta ADC, the inverting sample/hold circuit inverts the input the 2nd Incremental Sigma Delta ADC, which is the output of switched capacitor integrator within the 1st Incremental Sigma Delta ADC block. The increased active area is relatively small by the added analog circuit, because the digital circuit area is more large than analog. In this paper, a 14 bit Extended Counting Incremental Sigma-Delta ADC is implemented in $0.25{\mu}m$ CMOS process with a single 2.5 V supply voltage. The conversion speed is about 150 Ksamples/sec at a clock rate of 25 MHz. The 1 MSB is 0.02 V. The active area is $0.50\;x\;0.35mm^{2}$. The averaged power consumption is 1.7 mW.

• Journal of IKEEE
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• v.16 no.4
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• pp.343-348
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• 2012

A 11b 100KS/s Algorithmic ADC for Digital PFC controller is proposed. The proposed Algorithmic ADC structure for 11bit resolution is based on a cyclic architecture to reduce chip area and power consumption. The prototype Algorithmic ADC implemented with a 0.18um 1Poly-3Metal CMOS process shows a SNDR 66.7dB and ENOB 10.78bits. And the current consumption is about 780uA at 100KS/s and 5V. The occupied active die area is $0.27mm^2$.

• Transactions of Materials Processing
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• v.28 no.1
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• pp.34-42
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• 2019

In this study, various alloying elements (Cr, Sr, Ca, Cd) were added to improve the mechanical properties of ADC12 fabricated by a die casting process. The effect of alloying elements on the microstructure and mechanical properties were investigated. The phase analysis results of the modified ADC12 alloy with conventional ADC12 alloy, showed the similar characteristics of Al matrix, Si phase, $CuAl_2$ phase and the Fe intermetallic phase. As a result of the microstructure observation, the secondary dendrite arm spacing (SDAS) was shown to have decreased after the addition of the alloying elements. The eutectic Si phase, which existed as flake form in the conventional ADC12 alloy, was modified finely as a fiber form in the modified ADC12 alloy. It was observed that the $CuAl_2$ phase as the strengthening phase was relatively finely distributed in the modified ADC12 alloy. The Fe intermetallic appeared as a Chinese script shaped $Al_6$ (Mn,Fe) which is detrimental to mechanical properties in conventional ADC12 alloy. On the other hand, in the modified ADC12 alloy, polyhedral ${\alpha}-Al_{15}Si_2$ $(Fe,Mn,Cr)_3$ was observed. The tensile properties were improved in the modified ADC12 alloy. The yield strength and tensile strength increased by 12.4% and 10.0%, respectively, in the modified ADC12 alloy, and the elongation was also seen to have been increased. As a result of the pin on disk wear test, the wear resistance properties were also improved by up to about 7% in the modified ADC12 alloy. It is noted that the wear deformation microstructures were also observed, and it was found that the fine eutectic Si and strengthening phases greatly improved abrasion resistance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.