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Design of a Algorithmic ADC for Digital PFC Controller

Digital PFC Controller를 위한 Algorithmic ADC 설계

  • Jang, Ki-Chang (School of Electrical and Computer Engineering. University of Seoul) ;
  • Kim, Jin-Yong (School of Electrical and Computer Engineering. University of Seoul) ;
  • Hwang, Sang-Hoon (Samsung Electro-Mechanics Co., ltd.) ;
  • Choi, Joong-Ho (School of Electrical and Computer Engineering. University of Seoul)
  • Received : 2012.07.02
  • Accepted : 2012.11.27
  • Published : 2012.12.31

Abstract

A 11b 100KS/s Algorithmic ADC for Digital PFC controller is proposed. The proposed Algorithmic ADC structure for 11bit resolution is based on a cyclic architecture to reduce chip area and power consumption. The prototype Algorithmic ADC implemented with a 0.18um 1Poly-3Metal CMOS process shows a SNDR 66.7dB and ENOB 10.78bits. And the current consumption is about 780uA at 100KS/s and 5V. The occupied active die area is $0.27mm^2$.

본 논문에서는 Digital PFC Controller에 적합한 11비트 100KS/s의 Algorithmic ADC를 설계하였다. 설계한 Algorithmic ADC는 PFC controller에 적합한 11비트 해상도를 만족하면서 반복적인 순환구조의 동작으로 인해 전체 크기를 줄일 뿐 아니라 소비 전류를 최소화 할 수 있다. 본 논문의 Algorithmic ADC는 0.18um 1Poly-3Metal의 CMOS 공정으로 제작 되었으며 100KS/s의 동작 속도에 SNDR 66.7dB, ENOB 10.78비트의 성능을 가진다. 또한 소비전류는 5V 전원 전압에서 780uA이며 설계된 ADC의 칩 면적은 $0.27mm^2$이다.

Keywords

References

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