• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.7
• /
• pp.1442-1447
• /
• 2004

In this paper, a 6-Bit CMOS Folding and Interpolating AD Converter is presented. The converter is considered to be useful as an integrated part of a VLSI circuit handling both analog and digital signals as in the case of HDD or LAN applications. A built-in analog circuit for VLSI of a high-speed data communication requires a small chip area, low power consumption, and fast data processing. The proposed folding and interpolating AD Converter uses a very small number of comparators and interpolation resistors, which is achieved by cascading a couple of folders working in different principles. This reduced number of parts is a big advantage for a built-in AD converter design. The design is based on 0.25m double-poly 2 metal n-well CMOS process. In the simulation, with the applied 2.5V and a sampling frequency of 500MHz, the measurements are as follows: power consumption of 27mw, INL and DNL of $\pm$0.1LSB, $\pm$0.15LSB each, SNDR of 42dB with an input signal of 10MHz.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.5C
• /
• pp.378-385
• /
• 2008

This paper has been designed with CMOS Analog-to-Digital Converter(ADC) to use a high speed embedded system. It used flash ADC with a voltage estimator and comparator for background developed autozeroing. The speed of this architecture is almost similar to conventional flash ADC but the die size are lower due to reduced numbers of comparators and associated circuity. This ADC is implemented in a $0.25{\mu}m$ pure digital CMOS technology.

• 제어로봇시스템학회:학술대회논문집
• /
• 2000.10a
• /
• pp.31-31
• /
• 2000

In this paper, Ive design and test the V/F converter for KSR-III INS using commertial INC, VFC110, AD652. The test result shows that performance of AD652 is better than that of VFC110. Through the calibration of V/F converter, we show that the designed V/F converter has a good performance and is usable for KSR-III.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.12
• /
• pp.22-28
• /
• 2008

This paper designed a efficient 8-bit CMOS analog-to-digital converter(ADC) for an SOC(System On Chip) application. The architecture consists of two modified 4-bit full-flash ADCs, it has been designed using a more efficient architecture. This is to predict roughly the range in which input signal residers and can be placed in the proximity of input signal based on initial prediction. The prediction of input signal is made available by introducing a voltage estimator. For 4-bit resolution, the modified full-flash ADC need only 6 comparators. So a 8-bit ADC require only 12 comparators and 32 resistors. The speed of this ADC is almost similar to conventional full-flash ADC, but the die area consumption is much less due to reduce numbers of comparators and registors. This architecture uses even fewer comparator than half-flash ADC. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.5
• /
• pp.976-981
• /
• 2009

This paper proposed optimal design and microcontroller driver for driving the thin-type ultrasonic motor. To find the optimal size of the stator, motions of the motor were simulated using ATILA by changing length, width and thickness of the ceramics. Two sinusoidal waves which have 90 degree phase difference were needed for driving the thin-type motor. The thin-type ultrasonic motor driver was composed of microcontroller(Atmega128), push-pull inverter, encoder and AD-converter. Microcontroller generates four square waves which have variable frequency and 25[%] duty ratio in $20{\sim}150$[kHz]. The output signals of microcontroller were converted to sine wave and cosine wave by push-pull inverter and were applied to the thin-type ultrasonic motor. The encoder and AD-converter were used for maintaining speed of the thin-type ultrasonic motor. The AD-converter controlled DC voltage of inverter in accordance with output signal of encoder. Using the driver, characteristics of the motor as speed and torque were measured.

• Journal of the Korea Safety Management & Science
• /
• v.17 no.3
• /
• pp.363-370
• /
• 2015

In this paper, the control technique of the stepping motor using back electromotive force(B-EMF) without encoder is investigated. The stepping motor generally uses the rotary encoder to detect the rotor position. Since this method increases the cost and the motor configuration size, the new closed-loop control method applied for the B-EMF was implemented by using current detect circuit, AD-converter, and micro controller unit(MCU). The control loop of stepping motor became very simplified. The current change of stepping motor measured by the amplifier was measured and analyzed, when the missing step is occurred. Based on the data from current feedback, position errors were compensated and confirmed by using AD-converter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.05a
• /
• pp.220-223
• /
• 2012

Generally, SAW device, which uses Time Domain Sampling, requires high speed AD converter because SAW device (TDS) needs high sampling speed as much as its high data speed. However, the high price of AD converter discourages makers from using it. On the other hand, SAW device, which uses Frequency Domain Sampling, does not required high speed AD converter because SAW device (FDS) does not need high sampling speed. It is very efficient in price comparison to its performance because high processing speed of SAW device (FDS) can be implemented using low price Embedded Systems. The purpose of the thesis is to solve the issues above by designing and realizing SAW device (FDS) using SAW sensor for TDS.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.10a
• /
• pp.312-315
• /
• 2012

Generally, SAW device, which uses Time Domain Sampling, requires high speed AD converter because SAW device (TDS) needs high sampling speed as much as its high data speed. However, the high price of AD converter discourages makers from using it. On the other hand, SAW device, which uses Frequency Domain Sampling, does not required high speed AD converter because SAW device (FDS) does not need high sampling speed. It is very efficient in price comparison to its performance because high processing speed of SAW device (FDS) can be implemented using low price Embedded Systems. The purpose of the thesis is to solve the issues above by designing and realizing SAW device (FDS) using SAW sensor for TDS.

• Journal of IKEEE
• /
• v.23 no.2
• /
• pp.636-641
• /
• 2019

A simple resistance deviation-to-time period converter is proposed for interfacing resistive half-bridge sensors. It consists of two 2nd generation current conveyors(CCIIs). The proposed converter has simpler circuit configuration than the conventional converters using operational amplifiers or operational transconductance amplifiers(OTAs). The proposed converter was simulated using CCII implemented with AD844 IC chips. The simulation results show that the converter has a conversion sensitivity of $0.01934ms/{\Omega}$ over a range of $100-500{\Omega}$ resistance deviations and a linearity error less than ${\pm}0.002%$.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.4
• /
• pp.826-832
• /
• 2004

A CMOS 8 bit folding and interpolating ADC for an embedded system inside VLSI is presented in this paper. This folding ADC uses the 2 stage architecture for improving of nonlinearity. repeating the folding and interpolating twice. At a proposed structure, a transistor differential pair operates on the second folder. A ADC with 2 stage architecture reduces the number of comparators and resisters. So it is possible to provide small chip size, low power consumption and high operating speed. The design technology is based on fully standard 0.25m double-Poly 2 metal n-well CMOS Process. The simulated Power consumption is 45mW with an applied voltage of 2.5V and sampling frequency of 250MHz. The INL and DNL are within <ㅆㄸㅌ>$\pm$0.2LSB, respectively. The SNDR is approximately 45dB for input frequency of 10MHz.