1 |
R. Jacob Baker, "CMOS Circuit Design, Layout, and Simulation," IEEE Press, pp.932-1015, 2005
|
2 |
C.-W. Hsu and T.-H. Kuo, "6-bit 500 MHz flash A/D converter with new design techniques," in Proc. of IEEE Conf. on Circuits Syst., pp.460-464, Vol.150, No 5. October 2003
|
3 |
Steven M. Rubin, " Using Electric VLSI Design system," http://www.staticfreesoft.com/
|
4 |
Mike Engelhardt, "About LT spice/Switcher CAD III,"http://www.linear.com/designtools/software/
|
5 |
Marcel J. M. Pelgrom, A. C. Jeannet v. Rens, Maarten Vertregt, and Marcel B. Dijkstra, "A 25-Ms/s 8-bit CMOS A/D Converter for Embedded Application," IEEE Solid-State Circuits, Vol.29, No.8, pp.879-886, August 1994
DOI
ScienceOn
|
6 |
Koichi Ono, Tatsuji Matsuura, Eiki Imaizumi, Hisashi Okazawa, and Ryuushi Shimokawa, "Error Suppressing Encode Logic of FCDL in a 6-b Flash A/D Converter," IEEE Journal of Solid-state circuits, Vol.32, No.9, pp.1460-1464, 1997
DOI
ScienceOn
|
7 |
Sherman, L, "Fast CMOS A/D chip samples inputs". Electron. Design, pp.149-159. July 8, 1982
|
8 |
Bruce Peetz, Brian D. Hamilton, and James Kang, "An 8-bit 250 Megasample per Secoung Analog-to-Digital Converter: Operation Without a Sample and Hold," IEEE Solid-State Circuits, Vol.sc21, No.6, pp.997-1002, December 1986
|
9 |
Marc L. Simpson, and Ronald D. Williams, "A Simple Design Methodology for Table Flash A/D Converter Output Encoding," IEEE Trans. on Instrumentation and Measurement, Vol.37, No.4, pp.605-609, December 1988
DOI
ScienceOn
|
10 |
Michael J. Demler, "High-speed Anolog-To-Digital Conversion", Academic Press, pp.24 - 67, 1991
|