• Korean Journal of Logic
• /
• v.3
• /
• pp.27-51
• /
• 2000

이글의 기본적인 목적은 2치를 포함한 다치 논리 체계들간의 관계를 검토하는 데 있다. 이를 위하여 여기서는 명제를 대상으로 한 형식 의미 해석체계들 간에 고러해야 할 의미론적 확장 개념을 분명히 하였다. 구체적으로 다음의 두 작업이 수행되었다 첫째로 2치와 다치 논리 또는 다치 논리들간에 적용될 만한 의미론적 확장 개념을 의미해석의 바탕을 이루는 진리치 함수와 진리연산에 맞게 정의하였다. 둘째로 정의의 적합성을 확장, 비확장 사례 증명을 통해 예증해 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.1
• /
• pp.76-82
• /
• 2002

This paper presents a quaternary-binary decoder, a quaternary logic current buffer, and a quaternary logic full-adder using current-mode multiple-valued logic CMOS circuits. Proposed full-adder requires only 15 MOSFET, 60.5% and 48.3% decrease of devices are achieved compared with conventional binary CMOS full-adder and Current's full-adder. Therefore, decrease of area and internal nods are achieved. Designed circuits are simulated and verified by HSPICE. Proposed full-adder has 1.5 ns of propagation delay and 0.42㎽ of power consumption. Also, proposed full-adder can easily adapted to binary system by use of encoder, designed decoder and designed current buffer.

• Korean Journal of Logic
• /
• v.17 no.3
• /
• pp.441-461
• /
• 2014

This paper deals with one sort of Kripke-style semantics for three-valued paraconsistent logic: algebraic Kripke-style semantics. We first introduce two three-valued systems, define their corresponding algebraic structures, and give algebraic completeness results for them. Next, we introduce algebraic Kripke-style semantics for them, and then connect them with algebraic semantics.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.10
• /
• pp.52-62
• /
• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• Korean Journal of Logic
• /
• v.18 no.1
• /
• pp.65-83
• /
• 2015

This paper deals with non-algebraic Kripke-style semantics for three-valued paraconsistent logic: set-theoretical Kripke-style semantics. We first recall two three-valued paraconsistent systems. We next introduce set-theoretical Kripke-style semantics for them.

• Journal of IKEEE
• /
• v.9 no.1 s.16
• /
• pp.1-6
• /
• 2005

This paper proposes a high performance multiplier using CMOS multiple-valued logic circuits. The multiplier based on the Modified Baugh-Wooley algorithm is designed with current-mode CMOS quaternary logic circuits. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion block), current-mode quaternary logic full-adder block, and quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. This multiplier can easily adapted to the binary system by the encoder and the decoder. This circuit is designed with 0.35um standard CMOS process at 3.3V supply voltage and 5uA unit current. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of IKEEE
• /
• v.8 no.1 s.14
• /
• pp.47-53
• /
• 2004

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are composed with ternary voltage mode NMAX, NMIN, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.35um CMOS technology and 3.3Volts supply voltage. The architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.3
• /
• pp.613-623
• /
• 2011

In this paper, we present a method on the construction of quinternary logic circuits using Perfect shuffle. First, we discussed the input-output interconnection of quinternary logic function using Perfect Shuffle techniques and Kronecker product, and designed the basic cells of performing the transform matrix and the reverse transform matrix of quinternary Reed-Muller expansions(QRME) using addition circuit and multiplication circuit of GF(5). Using these basic cells and the input-output interconnection technique based on Perfect Shuffle and Kronecker product, we implemented the quinternary logic circuit based on QRME. The proposed design method of QRME is simple and very efficient to reduce addition circuits and multiplication circuits as compared with other methods for same logic function because of using matrix transform based on modular structures. The proposed design method of quinternary logic circuits is simple and regular for wire routing and possess the properties of concurrency and modularity of array.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.3
• /
• pp.491-499
• /
• 2007

In this paper, we present a design method of the ternary logic circuits based on Reed-Muller expansions. The design method of the presented ternary logic circuits checks the degree of each variable for the coefficients of Reed-Holler Expansions(RME) and determines the order of optimal control input variables that minimize the number of Reed-Muller Expansions modules. The order of optimal control input variables is utilized the computation of circuit cost matrix. The ternary logic circuits of the minimized tree structures to be constructed by RME modules based on Reed-Muller Expansions are realized using the computation results of its circuit cost matrix. This method is only performed under unit time in order to search for the optimal control input variables. Also, this method is able to be programmed by computer and the run time on programming is $3^n$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.3 s.333
• /
• pp.43-50
• /
• 2005

In this paper, quaternary logic gates using Down literal circuit(DLC) has been designed, and then synchronous Quaternary un/down counter using those gates has been proposed The proposed counter consists of T-type quaternary flip flop and 1-of-2 threshold-t MUX, and T-type quaternary flip flop consists of D-type quaternary flip flop and quaternary logic gates(modulo-4 addition gates, Quaternary inverter, identity cell, 1-of-4 MUX). The simulation result of this counter show delay time of 10[ns] and power consumption of 8.48[mW]. Also, assigning the designed counter to MVL(Multiple-valued Logic) circuit, it has advantages of the reduced interconnection and chip area as well as easy expansion of digit.