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http://dx.doi.org/10.6109/jkiice.2007.11.3.491

Design of Ternary Logic Circuits Based on Reed-Muller Expansions  

Seong, Hyeon-Kyeong (상지대학교 컴퓨터정보공학부)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.11, no.3, 2007 , pp. 491-499 More about this Journal
Abstract
In this paper, we present a design method of the ternary logic circuits based on Reed-Muller expansions. The design method of the presented ternary logic circuits checks the degree of each variable for the coefficients of Reed-Holler Expansions(RME) and determines the order of optimal control input variables that minimize the number of Reed-Muller Expansions modules. The order of optimal control input variables is utilized the computation of circuit cost matrix. The ternary logic circuits of the minimized tree structures to be constructed by RME modules based on Reed-Muller Expansions are realized using the computation results of its circuit cost matrix. This method is only performed under unit time in order to search for the optimal control input variables. Also, this method is able to be programmed by computer and the run time on programming is $3^n$.
Keywords
Ternary logic circuit; Reed-Muller Expansions; RME module; circuit cost matrix;
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