Browse > Article

The Design of the Ternary Sequential Logic Circuit Using Ternary Logic Gates  

윤병희 (인하대학교 전자공학과)
최영희 (인하대학교 전자공학과)
이철우 (인하대학교 전자공학과)
김흥수 (인하대학교 전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.10, 2003 , pp. 52-62 More about this Journal
Abstract
This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.
Keywords
Neuron MOS; DLC; Ternary gate; D-F/F; Register;
Citations & Related Records
연도 인용수 순위
  • Reference
1 A. Hueng and H. T. Mouftah, Depletion/enhancement CMOS for a low power family of three valued logic circuits, IEEE J. Solid-State Circuits, vol. SC-20, pp. 609-616, Apr. 1985
2 Wang Shoujue, The high speed ternary logic gates based on the multiple ${\Beta}$ transistors, Proc. 25th ISMVL, pp. 178-181, May. 1995   DOI
3 A. H. M. SHOUSHA, Switched-curent CMOS ternay logic circuits' INT. J. ELECTRONICS, vol. 79, No. 5, pp. 617-625, 1995   DOI   ScienceOn
4 Yasunori Nagata., Design of an Asynchronous Digital System with B-temary Logic' Proc. 27th ISMVL, pp. 256-271, May. 1997   DOI
5 Prosser. F., Wu, X., Chen, X., CMOS ternary flip-flops and their applications, Computers and Digital Techniques, IEE Proc. vol.135, pp. 266-272, Sep. 1988
6 Current, K.W., Multiple-valued logic memory circuit, Int. Journal of electronics, pp. 547-555, 1995, 78(3)   DOI   ScienceOn
7 Moroi Inaba, Realization of NMAX and NMIN Functions with Multi-Valued voltage Com-parator, Proc. 31th ISMVL, pp. 27-32, May. 2001   DOI
8 Jing Shen, Multi valued logic pass gate network using neuron MOS transistors, Proc. 30th ISMVL, May 2000   DOI
9 Jing shen, 'Down literal circuit with neuron MOS transistor and its applications, Proc. 2th ISMVL, May 1999   DOI
10 K. C. Smith, The prospects for multi-valed logic: A technology and applications view, IEEE Trans. Comput., vol. C-30, pp. 619-634, Sept. 1981   DOI   ScienceOn
11 T. Shibata, Neuron MOS binary-logic integrated circuits-part I : Design fundamentals and soft-hardware-loguc circuit implementation, IEEE Trans electron device, vol. 40, no. 3, pp. 570-576, Mar. 1993   DOI   ScienceOn
12 H. T. Mouftah and I. B. Jorden, Integrated circuits for ternary logic, IEEE Proc. ISMVL, May 1974, pp. 285-302
13 H. T. Mouftah and K. C. Smith, Design and implementation of three-valued logic systems with MOS. integrated circuits, Proc. Inst. Elec. Eng., vol. 127, pt. G, pp. 165-168, Aug. 1980
14 S. L. Hurst, Multi-valued logic-Its status and its future, IEEE Trnas. Comput., vol. C-33, pp. 1160-1179, 1984   DOI   ScienceOn
15 X. W. Wu and F. P. Prosser, CMOS termary logic circuits, Proc. Inst. Elec. Eng., vol. 137, pt. G, pp. 211-217, Feb. 1990