• Journal of the Korean Institute of Intelligent Systems
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• v.18 no.5
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• pp.611-616
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• 2008

Error correcting codes (ECCs) are commonly used to protect against the soft errors. Single error correcting and double error detecting (SEC-DED) codes are generally used for this purpose. The proposed approach in this paper selectively reduced power consumption, delay, and area in single-error correcting, double error-detecting checker circuits that perform memory error correction. The multi-objective genetic algorithm is employed to solve the non -linear optimization problem. The proposed method allows that user can choose one of different non-dominated solutions depending on which consideration is important among them. Because we use multi-objective genetic algorithm, we can find various dominated solutions. Therefore, we can choose the ECC according to the important factor of the power, delay and area. The method is applied to odd-column weight Hsiao code which is well- known ECC code and experiments were performed to show the performance of the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.12
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• pp.991-997
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• 2013

A new frequency tuning scheme and a transconductor with a wide tuning range and low harmonic distortion is presented. This frequency tuning technique is based on the relationship between the time-constant and the elapsed times in charging a capacitor up to a certain level. Its structure is as simple as that of a conventional tuning scheme using a VCF(Voltage-Controlled Filter) and it does not need a pure sine wave but uses a CLK(Clock) pulse as a reference signal, which is easily obtained from on-chip system clocks or external X-tal oscillators. When a certain reference CLK is given, without complex capacitor arrays the pole frequency of the filter can be controlled continuously in the frequency domain. Simulation results are presented to confirm the operation of the proposed approach.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.84-92
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• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.83-91
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• 1993

In the digital transmission system, cyclic redundancy check(CRC) code is widely used because it is easy to be implemented and has good performance in error detection. CRC code generator consists of several shift registers and modulo 2 adders. After manipulation of input data stream in the encoder, the remaining value of shift registers becomes CRC code. At the receiving side, error can be detected and corrected by CRC codes immediately transmitted after data stream. But, in the high speed system such as an A TM switch, it is difficult to implement the serial CRC encoder because of speed limitation of available semiconductor devices. In this paper, we propose the efficient parallel CRC encoder and syndrome calculator to solve the speed problem in implementing these functions using the existing semiconductor technology.

• 전자공학회논문지 IE
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• v.45 no.3
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• pp.5-12
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• 2008

We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.1
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• pp.52-60
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• 1997

A 23GHz 2-stage LNA was designed using MPIE numerical analysis and microwave CAD EEsof softwares. The basic circuit was designed by EEsof tools but analyzed more precisely using numerical MPIE tools and modified. The matching sections of the input and output terminals were designed with paralledl coupled filter-type lines, these matching sections perform impedance matching and DC blocking, more over have the advantages of small discontinuities and small errors in the design process. The FET chip is directly attached to the ground metal. The designed LNA gives 15.2dB gain and 2.7dB noise figure. without considering 1.8dB loss of connectors. These results validate our design process and matching schemes and fabrication technologies over the 20GHz frequency range.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.33-35
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• 2018

본 논문에서는 Quasi-Watkins-Johnson(qWJ) 인버터를 제안한다. 단상 qWJ 인버터는 기존의 Watkins-Johnson(WJ) 인버터에서 간단한 회로 수정을 통해 제안되며, 기존의 WJ 인버터의 모든 장점을 유지한다. 제안한 인버터는 모든 능동 스위치가 비절연형 게이트 구동을 하므로 게이트 구동회로의 부담을 덜어주고 기존 방식에 비해 적은 비용과 작은 크기로 구현할 수 있다. 또한, 제안한 인버터는 기존의 하프-브릿지 인버터의 출력전압보다 더 큰 출력전압을 가진다. 3상 qWJ 인버터는 출력전압이 입력전압의 2배까지 승압이 가능하다. 계통연계형 태양광 시스템에 적용 시, 기존의 3상 전압형 인버터는 누설전류로 인해 안정성에 문제가 생길 수 있지만, 제안한 인버터는 누설전류에 의한 문제가 생기지 않는다. 그러므로 제안한 인버터는 누설전류를 줄이기 위한 추가적인 회로가 필요하지 않고 적은 비용과 작은 사이즈로 계통연계형 태양광 인버터 시스템을 구현할 수 있다. 이러한 장점들은 3상 qWJ 인버터에서 더욱 현저하게 드러난다. 1kW의 시제품을 제작하여 제안한 인버터의 성능을 검증하였다.

• Proceedings of the KSAR Conference
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• 2001.03a
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• pp.84-84
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• 2001

한우 농가의 다두화 사육규모에 적합한 번식관리모델 제시 및 수태율 증진을 위한 발정제어 방법을 개발하고자 수행하였다. 1. 년중 번식구의 분만간격은 412.9일, 수태당종부횟수 1.76회에 반하여 계절번식 I구와 II구는 각각 370.4일과 1.51회, 376.5일과 1.48회로 나타났다. 2. 송아지 생산율에 있어서 년중번식구 78.2%(174/184), 계절번식 I구 71.7%(99/138)에 비해 계절번식 II구에서는 79.2%(172/217)로 효율이 다소 높았다. 3. 발정유기방법별 동기화율에 있어서 PGF$_2$$_{\alpha}$ 2회 투여법에서 68.1%(141/207), PRID 삽입법 71.42%(15/21), CIDR 삽입법 86.3%(33/38)에 비해 GnRH-PGF$_2$$_{\alpha}$-GnRH 처리법은 93.1%(216/232)로 효율이 가장 높았다. 4. 발정유기방법별 1회 수정수태율은 PGF$_2$$_{\alpha}$ 2회 투여법 55.1%(64/l16), PRID 삽입법 54.0%(20/37), CIDR 삽입법 58.6%(17/29), 일괄수태법 58.8%(60/102)로 나타났고, 수태율은 각각 75%(87/116), 81%(30/37), 89.6%(26/29), 91.1%(93/102)였다. 5. 일괄수태 처리후 수정시점에 따른 수태율은 최종 GnRH 투여후 16~20 시간구가 65.3%로 가장 좋았다.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.217-221
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• 2007

This paper deals with the robust nonlinear controller design using output feedback for a Chua circuit which is one of the well-known nonlinear models. First, an exosystem for reference signal tracking is defined, and error dynamic equations are derived from the differentiation of the output tracking error equation. The normal sliding surface is modified using the integral type servo compensator. The parameters in the equations of the modified sliding surface and servo compensator are determined by using the Hurwitz condition of stability. Especially the error signals can't be obtained directly from the output because all parameters are assumed unknown. So instead, a high gain observer is designed. From this estimated error signals, a stabilizing controller is designed. Simulation is done for demonstrating the effectiveness of the suggested algorithm.

• Journal of the Korean Society of Marine Environment & Safety
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• v.13 no.2 s.29
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• pp.169-172
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• 2007

This paper presents circuit models and control algorithms of distributed generation system(DGS) which consists of Z-type converter and PWM inverter. Z-type converter which employs both the L and C passive components and shoot-through zero vectors instead qf the conventional DC/DC converter in order to step up DC-link voltage. Discrete time sliding mode control with the asymptotic observer is used for current control. This system am be used for power conversion of DC renewable energy.