• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.384-392
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• 2003

The algorithm for calculating the base-collector breakdown voltage of NPN BJT for integrated circuits is proposed. The method of three-dimensional mesh generation to minimize the time required for device simulation is presented and the method for calculating the breakdown voltage using solutions of the Poisson´s equation is presented. To verify the proposed method, the breakdown voltage between base and collector of NPN BJT using 20V process and 30V process is compared with the measured data. The breakdown voltage from the proposed method of NPN BJT using 20V process shows an averaged relative error of 8.0% compared with the measured data and the breakdown voltage of NPN BJT using 30V process shows an averaged relative error of 4.3% compared with the measured data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.1-9
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• 2004

Analytical expressions for breakdown voltages of abrupt pn junction in GaP, GaAs and InP of III-V binary semiconductors was induced. Getting analytical breakdown voltage, effective ionization coefficients were extracted using ionization coefficient parameters for each materials. The result of analytical breakdown voltages followed by ionization integral agrees well with numerical and experimental results within 10% in error.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.100-105
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• 1994

Analytical expressions for the breakdown voltage and the optimum drift region length (L$_{dr}$) of SOI (Silicon-On-Insulator) pn diodes are derived in terms of the doping concentration and the thickness of the n- drift region and the buried oxide thickness. The optimum L$_{dr}$ is obtained from the condition that the breakdown voltage of the vertical electric field of n+n- junction equals to the of the lateral electric field of n+n-p+ junction. Analytical results agree reasonably with the numerical simulations using PISCESII.

• 전자공학회논문지 IE
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• v.44 no.1
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• pp.10-14
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• 2007

Analytical expression for breakdown voltages of InP diodes is induced by employing the effective ionization coefficient extracted from ionization coefficients for electron and hole in InP. The analytical results for breakdown voltage are compared with numerical and experimental results for the doping concentration, $N_D=6\times10^{14}cm^{-3}\sim3\times10^{17}cm^{-3}$. The analytical results show good agreement with the numerical data. Good fits with the experimental results are found for the breakdown voltages within 10% in error at each doping concentration.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.59-60
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• 2006

원통형 PN접합의 Baliga의 해석적인 항복전압에 대한 근사식을 유도하였다. 근사식은 접합길이, $r_j$와 공핍층 깊이, $W_{pp}$의 비 ($r_i/W_{pp}$)가 0.1보다 작은 경우 Baliga식과 잘 일치하였다. 농도에 대한 원통형 접합의 항복전압의 민감도를 유도하였으며, 근사식을 사용한 경우가 Baliga식의 경우보다 민감도식이 더 간단하기 때문에, 민감도를 고려한 소자 설계 시 활용될 수 있으리라 기대된다. 민감도 식을 이용하여 설계한 결과 항복전압의 편차가 10% 이내로 제어하기 위해서는 도핑농도가 $10^{15}cm^{-3}$이고 접합깊이가 $5{\mu}m$ 인 원통형 접합인 경우 농도 편차가 12.8%이내 이어야한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.9-18
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• 2005

Analytical expressions for breakdown voltages of abrupt $p^{+}n$ junction of Si, GaAs, InP and In$In_{0.53}Ga_{0.47}AS$ were induced. Getting analytical breakdown voltages, effective ionization coefficients were extracted using lucky drift parameters of Marsland for each materials. The results of analytical breakdown voltages followed by ionization integral agreed well with experimental result within 10$\%$ in error for the doping concentration in the range of $10^{14}cm\;^{-3}\~5\times10\;^{17}cm\;^{-3}$.

• Journal of Advanced Navigation Technology
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• v.21 no.5
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• pp.501-507
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• 2017

When zenor diode load current is necessary to be controlled by input voltage as a circuit load, existing voltage controlling method cannot be applied to it because the output current of zenor diode is changed due to breakdown voltage variations. We propose input voltage controlled output current source regardless of zenor breakdown voltage variation due to degradation resulted from severe current applied electronic component life test as a circuit load in this paper. We show breakdown voltage characteristics of this zenor diode circuit through simulation, applying adequate values for each component in order to verify the circuit composed of that method, and then show the result in which output current is controlled by input voltage. We confirmed the output current varies proportional to input voltage, and developed circuit shows a constant value independent of zenor diode breakdown voltage variations due to component degradations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.6
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• pp.1460-1464
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• 2010

In the paper, the breakdown voltage of Trench D-MOSFET have been analyzed by using MircoTec. The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high-integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. A Trench MOSFET is the most preferred power device for high voltage power applications. The oxide thickness and doping concentration in Trench MOSFET determines breakdown voltage and extensively influences on high voltage. We have investigated the breakdown voltage characteristics according to variation of doping concentration from $10^{15}cm^{-3}$ to $10^{17}cm^{-3}$ in this study. We have also investigated the breakdown voltage characteristics according to variation of oxide thickness and junction depth.

• Journal of the Korean Vacuum Society
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• v.22 no.6
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• pp.335-340
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• 2013

This paper is for the simulation design to enhance the breakdown voltage of MHEMTs with an InP-etchstop layer. Gate-recess and channel structures has been simulated and analyzed for the breakdown of the MHEMT devices. The fully removed recess structure at the drain side of MHEMT shows that the breakdown voltage enhances from 2 V to almost 4 V as the saturation current at gate voltage of 0 V is reduced from 90 mA to 60 mA at drain voltage of 2 V. This is because the electron-captured negatively fixed charges at the drain-side interface between the InAlAs barrier and the $Si_3N_4$ passivation layers deplete the InGaAs channel layer more and thus decreases the electron current passing the channel layer and thus the impact ionization in the channel become smaller. In addition, the replaced InGaAs/InP composite channel with the same thickness in the same asymmetrically recessed structure increases the breakdown voltage to 5 V due to the smaller impact ionization and mobility of the InP layer at high drain voltage.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1128-1129
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• 2015

4H-SiC는 차세대 전력용 반도체로서 고전압, 고전류, 고온 동작에 적합하여 각광을 받고 있다. 전력용 반도체의 항복전압 개선하기 위하여 활성 (active) 영역의 주위에 설계하는 접합마감 (junction termination) 영역의 설계가 필수적이다. P+ 이온주입 및 활성화가 어려운 SiC 특성상 $5{\mu}m$보다 깊은 P+ 접합을 구현하기 어려운 특성상 기존 P+ FLR의 접합마감 소자는 항복전압을 개선하기 어렵다. 접합마감 소자의 항복전압을 효과적으로 증가시키기 위하여 트렌치를 설계하였다. 기존 접합마감 소자의 길이와 항복은 $7{\mu}m$와 473.0 V이지만, 제안된 접합마감 소자의 길이와 항복전압은 $5{\mu}m$와 993.4 V로 우수하였다.