• Journal of the Korean Society for Nondestructive Testing
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• v.21 no.6
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• pp.650-657
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• 2001

This paper explains the process of designing a shielded encircling remote field eddy current (RFEC) probe to inspect nuclear fuel cladding tubes and investigates resulting signal characteristics. To force electromagnetic energy from exciter coil to penetrate into the tube, exciter coil is shielded outside by laminations of iron insulated electrically from each other. Effects of shielding and the proper operating frequency are studied by the finite element analysis and the location for sensor coil is decided. However, numerically simulated signals using the designed probe do not clearly show the defect indication when the sensor passes a defect and the other indication appeared as the exciter passes the defect is affected by the shape of shielding structure, which demonstrates that the sensor is directly affected by exciter fields. For this reason, the sensor is also shielded outside and this shielding dramatically improves signal characteristics. Numerical modeling with the finally designed probe shows very similar signal characteristics to those of inner diameter RFEC probe. That is, phase signals show almost equal sensitivity to inner diameter and outer diameter defects and the linear relationship between phase signal strength and defect depth is observed.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.22 no.4
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• pp.335-343
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• 2012

As a matter of fact, it has been not allowed to modify the shape of a vehicle body skeleton since the technical definition for the structure was fixed and the corresponding molds were developed. By the way, if it is available to apply an alternative to reinforce the skeleton without changing its mold, it must be much flexible to improve the performance qualities relevant to not only NVH(noise, vibration and harshness) but also crash and durability. Recently, a solution of so-called composite body becomes available for the need. We present a design method to insert the composite body inside a vehicle body skeleton in order to improve a structure-borne noise at the idle condition. The algorithms, topology optimization and design sensitivity analysis, are applied to mainly search the sensitive structural sections in the body skeleton and to extract the target stiffness of the sections. Inserting the composite bodies into the sensitive portions, it is predicted to achieve the countermeasures which can compromize the design availability in terms of the idle noise and weight. According to the validation result with test vehicles, the concerned noise transfer function is reduced and the idle booming noise is resultantly improved.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2011.10a
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• pp.279-284
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• 2011

The calculation of Zwicker's loudness which is needed for multiple frequency response with a fine frequency resolution using the finite element (FE) procedure usually requires significant computation time since a numerical solution must be obtained for each considered frequency. Furthermore, if the analysis is the basis for an iterative optimization procedure this approach imposes high computational cost. In this work, we present an efficient approach for obtaining Zwicker's loudness via the Pad$\acute{e}$ approximants and applying in an acoustical topology optimization procedure. The paper is focused on an efficient and accurate calculation of Zwicker's loudness, design sensitivity analysis, and the acoustical topology optimization method by using Pad$\acute{e}$ approximants. The paper compares the efficient algorithm to results obtained by a standard FEM. Comparison are made both in terms of accuracy and in terms of CPU-times needed for the calculation.

• The Journal of the Acoustical Society of Korea
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• v.26 no.6
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• pp.227-234
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• 2007

This paper describes a transmission method based on a single carrier with frequency domain equalization (SC-FDE) scheme with cyclic prefix(CP). The SC-FDE has similar features with orthogonal frequency division multiplexing(OFDM). Similar to OFDM, a SC-FDE system is computationally efficient since equalization is reformed on a block of data in the frequency domain. Especially, it has the advantage of low sensitivity to nonlinear distortion compared to OFDM. In this paper, we design a SC-FDE receiver using decision-directed method, and present simulation results.

• Journal of IKEEE
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• v.13 no.4
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• pp.63-68
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• 2009

The power management integrated circuit(PMIC) for CCD image sensor is presented in this study. A CCD image sensor is very sensitive against temperature. The temperature, that is heat, is generally generated by the PMIC with low efficiency. Since the generated heat influences performance of CCD image sensor, it should be minimized by using a PMIC which has a high efficiency. In order to develop the PMIC with high efficiency, the input stage is designed with synchronous type step down DC-DC converter. The operating range of the converter is from 5V to 15V and the converter is controlled using PWM method. The PWM control circuit consists of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit. The saw-tooth generator is designed with 1.2MHz oscillation frequency. The comparator is designed with the two stages OP Amp. And the error amplifier has 40dB DC gain and $77^{\circ}$ phase margin. The output of the step down converter is connected to input stage of the charge pump. The output of the charge pump is connected to input of the LDO which is the output stage of the PMIC. Finally, the PMIC, based on the PWM control circuit and the charge pump and the LDO, has output voltage of 15V, -7.5V, 3.3V and 5V. The PMIC is designed with a 0.35um process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.905-912
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• 2007

This paper proposes an efficient estimation and compensation scheme of IQ imbalance for OFDM-based WLAN systems in the presence of symbol timing error. Since the conventional scheme assumes perfect time synchronization, the criterion of the scheme used to derive the estimation of IQ imbalance is inadequate in the presence of the symbol timing error and the system performance is seriously degraded. New criterion and compensation scheme considering the effect of symbol timing error are proposed. With the proposed scheme, the IQ imbalance can be almost perfectly eliminated in the presence of symbol timing error. The bit error rate performance of the proposed scheme is evaluated by the simulation. In case of 54 Mbps transmission mode in IEEE 802.11a system, the proposed scheme achieves a SNR gain of 4.3dB at $BER=2{\cdot}10^{-3}$. The proposed compensation algorithm of IQ imbalance is implemented using Verilog HDL and verified. The proposed IQ imbalance compensator is composed of 74K logic gates and 6K bits memory from the synthesis result using 0.18um CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.