Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS ADC Based on High-Accuracy Integrated Capacitors

높은 정확도를 가진 집적 커페시터 기반의 10비트 250MS/s $1.8mm^2$ 85mW 0.13un CMOS A/D 변환기

  • Published : 2006.11.25
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Abstract

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

본 논문에서는 차세대 디지털 TV 및 무선 랜 등과 같이 고속에서 저전압, 저전력 및 소면적을 동시에 요구하는 고성능 집적시스템을 위한 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D 변환기 (ADC)를 제안한다. 제안하는 ADC는 요구되는 10b 해상도에서 250MS/s의 아주 빠른 속도 사양을 만족시키면서, 면적 및 전력 소모를 최소화하기 위해 3단 파이프라인 구조를 사용하였다. 입력단 SHA 회로는 게이트-부트스트래핑 (gate-bootstrapping) 기법을 적용한 샘플링 스위치 혹은 CMOS 샘플링스위치 등 어떤 형태를 사용할 경우에도 10비트 이상의 해상도를 유지하도록 하였으며, SHA 및 두개의 MDAC에 사용되는 증폭기는 트랜스컨덕턴스 비율을 적절히 조정한 2단 증폭기를 사용함으로써 10비트에서 요구되는 DC 전압 이득과 250MS/s에서 요구되는 대역폭을 얻음과 동시에 필요한 위상 여유를 갖도록 하였다. 또한, 2개의 MDAC의 커패시터 열에는 소자 부정합에 의한 영향을 최소화하기 위해서 인접신호에 덜 민감한 향상된 3차원 완전 대칭 구조의 커패시터 레이아웃 기법을 제안하였으며, 기준 전류 및 전압 발생기는 온-칩 RC 필터를 사용하여 잡음을 최소화하고, 필요시 선택적으로 다른 크기의 기준 전압을 외부에서 인가할 수 있도록 설계하였다. 제안하는 시제품 ADC는 0.13um 1P8M CMOS 공정으로 제작되었으며, 측정된 DNL 및 INL은 각각 최대 0.24LSB, 0.35LSB 수준을 보여준다. 또한, 동적 성능으로는 200MS/s와 250MS/s의 동작 속도에서 각각 최대 54dB, 48dB의 SNDR과 67dB, 61dB의 SFDR을 보여준다. 시제품 ADC의 칩 면적은 $1.8mm^2$이며 전력 소모는 1.2V 전원 전압에서 최대 동작 속도인 250MS/s일 때 85mW이다.

Keywords

References

  1. B. Vaz, J. Goes, and N. Paulino, 'A 1.5-V 10-b 50 MS/s time-interleaved switched-opamp pipeline CMOS ADC with high energy efficiency,' in Symp. VLSI Circuits Dig. Tech. Papers, June 2004, pp. 432-435
  2. S. T. Ryu, B. S. Song, and K. Bacrania, 'A 10b 50MS/s pipelined ADC with opamp current reuse,' in ISSCC Dig. Tech. Papers, Feb. 2006, pp. 216-217 https://doi.org/10.1109/ISSCC.2006.1696119
  3. H. C. Choi, J. H. Kim, S. M. Yoo, K. J. Lee, T. H. Oh, M. J. Seo, and J. W. Kim, 'A 15mW $0.2mm^2$ 10b 50MS/s ADC with wide input range,' in ISSCC Dig. Tech. Papers, Feb. 2006, pp. 226-227 https://doi.org/10.1109/ISSCC.2006.1696124
  4. Y. I. Park, S. Karthikeyan, F. Tsay, and E. Bartolome, 'A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8V power supply,' in Proc. IEEE Int Symp. Circuits and Systems, May 2001, pp. 580-583 https://doi.org/10.1109/ISCAS.2001.921922
  5. B. M. Min, P. Kim, D. Boisvert, and A. Aude, 'A 69mW 10b 80MS/s pipelined CMOS ADC,' in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 324-325 https://doi.org/10.1109/ISSCC.2003.1234318
  6. O. Stroeble, V. Dias, and C. Schwoerer, 'An 80MHz 10b pipeline ADC with dynamic range doubling and dynamic reference selection,' in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 462-463 https://doi.org/10.1109/ISSCC.2004.1332794
  7. Y. I. Park, S. Karthikeyan, F. Tsay, and E. Bartolome, 'A 10b 100MSample/s CMOS pipelined ADC with 1.8V power supply,' in ISSCC Dig. Tech. Papers, Feb. 2001, pp. 130-131 https://doi.org/10.1109/ISSCC.2001.912573
  8. J. Li and U. K. Moon, 'A 1.8-V 67mW 10-bit 100MSPS pipelined ADC using time-shifted CDS technique,' in Proc. CICC, Sept. 2003, pp. 1468-1476 https://doi.org/10.1109/CICC.2003.1249430
  9. K. Honda, F. Masanori, and S. Kawahito 'A 1V 30mW 10b 100MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques,' in Symp. VLSI Circuits Dig. Tech. Papers, June 2006, pp. 276-277 https://doi.org/10.1109/VLSIC.2006.1705391
  10. S. M. Yoo, T. H. Oh, J. W. Moon, S. H. Lee, and U. K. Moon, 'A 2.5V 10b 120 MSample/s CMOS pipelined ADC with high SFDR,' in Proc. CICC, May 2002, pp. 441-444 https://doi.org/10.1109/CICC.2002.1012869
  11. M. Yoshioka, M. Kudo, K. Gotoh, and Y. Watanabe, 'A 10b 125MS/s 40mW pipelined ADC in 0.18um CMOS,' in ISSCC Dig. Tech. Papers, Feb. 2005, pp. 282-283 https://doi.org/10.1109/ISSCC.2005.1493979
  12. S. M. Yoo, J. B. Park, H. S. Yang, H. H. Bae, K. H. Moon, H. J. Park, S. H. Lee, and J. H. Kim, 'A 10b 150MS/s 123mW 0.18um CMOS pipelined ADC,' in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 326-327 https://doi.org/10.1109/ISSCC.2003.1234319
  13. M. Clara, A. Wiesbauer, and F. Kuttner, 'A 1.8V fully embedded 10b 160MS/s two-step ADC in 0.18um CMOS,' in Proc. CICC, May 2002, pp. 437-440
  14. J. Li, G. Manganaro, M. Courcy, and B. M. Min, 'A 10b 170MS/s CMOS Pipelined ADC Featuring 84dB SFDR without Calibration,' in Symp. VLSI Circuits Dig. Tech. Papers, June 2006, pp. 278-279
  15. S. C. Lee, G. H. Kim, J. K. Kwon, J. D. Kim, and S. H. Lee, 'Offset and dynamic gain-mismatch reduction techniques for 10b 200MS/s parallel pipeline ADCs,' in Proc. Eur. Solid-State Circuits Conf., Sept. 2005, pp. 531-534 https://doi.org/10.1109/ESSCIR.2005.1541677
  16. D. Kurose, T. Ito, T. Deno, T. Yamaji, and T. Itakura, '55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers,' in Proc. Eur. Solid-State Circuits Conf., Sept. 2005, pp. 527-530 https://doi.org/10.1109/ESSCIR.2005.1541676
  17. B. Hernes, A. Briskemyr, T. N. Andersen, F. Telsto, T. E. Bonnerud, and O. Moldsvor, 'A 1.2V 220MS/s 10b pipeline ADC implemented in 0.13um digital CMOS,' in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 256-257
  18. A. M. Abo and P. R. Gray, 'A 1.5-V, 10-u, 14.3-MS/s CMOS pipeline analog-to-digital converter,' IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999 https://doi.org/10.1109/4.760369
  19. A. Gothenberg and H. Tenhunen, 'Performance analysis of sampling switches in voltage and frequency domains using volterra series,' in Proc. IEEE Int. Symp. Circuits and Systems, May 2004, pp. 765-768 https://doi.org/10.1109/ISCAS.2004.1328307
  20. B. H. Min, Y. J. Cho, H. S. Chae, H. W. Park, and S. H. Lee, 'A 10b 100MS/s $1.4mm^2$ 56mW 0.18um CMOS A/D converter with 3-D fully symmetrical capacitors,' IEICE Trans. on Electronics, vol. E89-C, no. 5, pp. 630-635, May 2006 https://doi.org/10.1093/ietele/e89-c.5.630
  21. P. R. Gray and R. G. Meyer, 'MOS operational amplifier design-a tutorial overview,' IEEE J. Solid-State Circuits, vol. SC-17, no. 6, pp. 969-982, Dec. 1982 https://doi.org/10.1109/JSSC.1982.1051851
  22. K. H. Lee, Y. J. Cho, Y. H. Park, D. H. Sa, H. C. Choi, and S. H. Lee, 'A 14b 100MS/s $3.4mm^2$ 145mW 0.18um CMOS pipeline A/D converter,' in IEEE APCCAS, Dec. 2006. (invited) https://doi.org/10.1109/APCCAS.2006.342442
  23. Y. J. Cho, H. C. Choi, K. H. Lee, S. H. Lee, K. H. Moon, and J. H. Kim, 'A calibration-free 14b 70MS/s 0.13um CMOS pipeline ADC with high-matching 3-D symmetric capacitors,' in Proc. CICC, Sept. 2006. pp. 485-488
  24. Y. J. Cho, H. H. Bae, and S. H. Lee, 'An 8b 220MS/s 0.25um CMOS pipeline ADC with on-chip RC-filter based voltage references,' IEICE Trans. on Electronics, vol. E88-C, no. 4, pp. 768-772, April 2005 https://doi.org/10.1093/ietele/e88-c.4.768