References
- H. S. Lee, 'A 12-b 600ks/s digitally self-calibrated pipelined algorithmic ADC,' IEEE J. Solid-State Circuits, vol. 29, no. 4, pp. 509-515, April 1994 https://doi.org/10.1109/4.280701
- J. S. Wang and C. L. Wey, 'A 12-bit 100-ns/bit 1.9-mW CMOS switched-current cyclic A/D converter,' IEEE Trans. Circuits Syst. II, vol. 46, pp. 507-516, May 1999 https://doi.org/10.1109/82.769799
- K. Satou et al., 'A 12bit 1MHz ACD with 1mW power consumption,' in Proc. CICC, May 1994, pp. 515-518 https://doi.org/10.1109/CICC.1994.379670
- G. Promitzer, '12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1MS/s,' IEEE J. Solid-State Circuits, vol. 37, no. 7, pp. 1138-1143, July 2001 https://doi.org/10.1109/4.933473
- L. Cong and W. C. Black, 'A new charge redistribution D/A and A/D converter technique pseudo C-2C ladder,' in Proc. IEEE Midwest Symposium, vol. 1, pp. 498-501, Aug. 2000 https://doi.org/10.1109/MWSCAS.2000.951692
- J. Doyle, K. Gallagher, and C. Lyden, 'A low power 12-bit ADC for systems applications,' lEE colloquium, Sept. 1998, pp. 17/1-17/4
- B. P. Brandt and B. A. Wooley, 'A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion,' IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 1746-1756, Dec. 1991 https://doi.org/10.1109/4.104165
- J. Li, G. C. Ahn, D. Y. Chang, and U. K. Moon, 'A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR,' IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 960-969, April 2005 https://doi.org/10.1109/JSSC.2004.842866
- D. Y. Chang and S. H. Lee, 'Design Techniques for a Low-Power Low-Cost CMOS A/D Converter,' IEEE J. Solid-State Circuits, vol. 33, no. 8, pp. 1244-1248, Aug. 1998 https://doi.org/10.1109/4.705363
- B. L. Jeon and S. H. Lee, 'A 10b 50MHz 320MW CMOS A/D converter for video applications,' Transactions on Consumer Electronics, vol. 45, no. 1, pp. 252-258, Feb. 1999 https://doi.org/10.1109/30.754443
- S. T. Ryu, S. Ray, B. S. Song, G. H. Cho, and K. Bacrania, 'A 14b-linear capacitor self-trimming pipelined ADC,' in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 464-465 https://doi.org/10.1109/ISSCC.2004.1332795
- S. Y. Chuang and T. L. Sculley, 'A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter,' IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 674-683, June, 2002 https://doi.org/10.1109/JSSC.2002.1004571
- J. Guilherme et al., 'A pipeline 15-b 10Msample/s analog-to-digital converter for ADSL applications,' in IEEE International Symposium on Circuits and Systems, May 2001, pp. 396-399 https://doi.org/10.1109/ISCAS.2001.921876
- H. C. Liu, Z. M. Lee, and J. T. Wu, 'A 15b 20MS/s CMOS pipelined ADC with digital background calibration,' in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 454-455 https://doi.org/10.1109/ISSCC.2004.1332790
- E. Siragusa and I. Galton, 'A digitally enhanced 1.8V 15b 40MS/s CMOS pipelined ADC,' in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 452-453 https://doi.org/10.1109/ISSCC.2004.1332789
- H. C. Liu, Z. M. Lee, and J. T. Wu, 'A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration,' IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1047-1056, May 2005 https://doi.org/10.1109/JSSC.2005.845986
- S. Hisano and S. E. Sapp, 'A 16-bit, 20MSPS CMOS pipeline ADC with direct INL detection algorithm,' in Proc. IEEE CICC, Sept. 2003, pp. 417-420 https://doi.org/10.1109/CICC.2003.1249431
-
H. C. Choi, S. B. You, H. Y. Lee, H. J. Park, and J. W. Kim, 'A calibration-free 3V 16b 500kS/s 6mW
$0.5mm^2$ ADC with 0.13um CMOS,' in Symp. VLSI Circuits Dig. Tech. Papers, June 2004, pp. 76-77 -
Y. J. Cho and S. H. Lee, 'An 11b 70-MHz
$1.2-mm^2$ 49-mW 0.18-um CMOS ADC with on-chip current/voltage references,' IEEE Transactions on Circuit and Systems I, vol. 52, no. 10, pp. 1989-1995, Oct. 2005 https://doi.org/10.1109/TCSI.2005.853251 - D. J. Comer and D. T. Comer, 'Using the weak inversion region to optimize input stage design of CMOS op amp,' IEEE Transactions on Circuit and Systems II, vol. 51, pp. 8-14, Jan. 2004 https://doi.org/10.1109/TCSII.2003.821517
- C. Popa and D. Coada, 'A new linearization technique for a cmos differential amplifier using bulk-driven weak inversion MOS transistors,' in Symp. Signals Circuits and Systems, vol. 2, July 2003, pp. 589-592 https://doi.org/10.1109/SCS.2003.1227121
- E. Seevinck, E. A. Vittoz, M. du Plessis, T. Joubert, and W. Beetge, 'CMOS translinear circuits for minimum supply voltage,' IEEE Transactions on Circuit and Systems II, vol. 47, pp. 1560-1564, Dec. 2000 https://doi.org/10.1109/82.899656
- C. C. Enz and E. A. Vittoz, 'CMOS low-power analog circuit design,' Designing Low-Power Digital Systems, Emerging Technologies, pp. 79-133, May 1996 https://doi.org/10.1109/ETLPDS.1996.508872