• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.13-19
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• 2020

In this paper, we propose a multiplexer based scheme that performs modular AB² multiplication using redundant basis over finite field. Then we propose an efficient multiplexer based semi-systolic AB² multiplier using proposed scheme. We derive a method that allows the multiplexers to perform the operations in the cell of the modular AB² multiplier. The cell of the multiplier is implemented using multiplexers to reduce cell latency. As compared to the existing related structures, the proposed AB² multiplier saves about 80.9%, 61.8%, 61.8%, and 9.5% AT complexity of the multipliers of Liu et al., Lee et al., Ting et al., and Kim-Kim, respectively. Therefore, the proposed multiplier is well suited for VLSI implementation and can be easily applied to various applications.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.2
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• pp.99-107
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• 2003

This paper proposes a design for testability (DFT) and testability analysis method for register-transfer level (RTL) circuits. The proposed method executes testability analysis - controllability and observability - on the RTL circuit and determines the insertion points to enhance the testability. Then with the associated priority based on the testability, we insert only a few of the test multiplexers resulting in minimized area overhead. Experimental results shows a higher fault coverage and a shorter test generation time than the scan method. Also, the proposed method takes a shorter test application time required.

• The Journal of the Convergence on Culture Technology
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• v.6 no.2
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• pp.515-520
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• 2020

CMOS used in digital circuit design technology has reached the limit of integration due to quantum tunneling. Quantum-dot cellular automata (QCA), which can replace this, has many advantages such as low power consumption and fast switching speed, so many digital circuits of CMOS have been proposed based on QCA. Among them, the multiplexer is a basic circuit used in various circuits such as D-flip-flops and resistors, and has been studied a lot. However, the existing multiplexer has a disadvantage that space efficiency is not good. Therefore, in this paper, we propose a new multilayered multiplexer using cell interaction and D-latch using it. The multiplexer and D-latch proposed in this paper have improved area, cell count, and delay time, and have excellent connectivity and scalability when designing large circuits. All proposed structures are simulated using QCADesigner to verify operation.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2004.11a
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• pp.15-19
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• 2004

Domestic use, or embody program that transmit NMEA protocol using multi port as software and is using because there is no fee and product that develop NMEA protocol Multiplexer, import mounting for foreign climax present. These method is paid or there is problem that must make out special processing part in each application program. Also, each mountings that display NMEA protocol can cause double resources waste and damage etc. because manufacturing firm and platform are different. Can act separatively as single hardware module of reliable processing method and high efficiency to supplement this in this treatise, and because using design of optimized cue, heighten memory efficiency of module, and proposed NMEA protocol Multiplexer that can keep high trustability of Come on, deviation compass, echo sound, mountings of GPS and so on and real time communication that is main input sensor equipment about embodiment.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.290-292
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• 1998

가입자망은 원래 전화 서비스를 위해 사용되었으나 멀티미디어 서비스를 지원하기위해 x-DSL기술을 기반으로 하는 가입자망 광대역화에 관심을 가지게 되었다. 특히 멀티미디어 서비스 비대칭성을 이용한 ADSL기술이 각광 받고 있다. 이 기술을 이용한 ATM 서비스가 가능하게 되어 DSLAM이라 불리우는 엑세스 멀티플렉서 장비의 개발 중요성이 부각되고 있다. 본 논문에서는 DSLAM에서 사용할 수 있는 셀 지연변이를 줄일 수 있는 버퍼관리 기법과 각 트래픽 클래스의 최대 대역폭을 보장해 줄 수 있는 대역폭관리 기법을 제안한다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2008.04a
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• pp.294-298
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• 2008

이메본 논문은 GP 트리의 노드포화도를 제어함으로써 트리의 구조공간에서 효율적인 개체 분포를 유도하는 GP 진화연산자를 제안한다. 특정 영역으로의 트리 개체의 분포가 성능에 미치는 영향을 검증하고 진화과정에서 나타나는 군집내의 개체 다양성과의 관계를 분석한다. 제안된 진화연산자를 회귀다항식, 멀티플렉서, 짝수 패리티의 3가지 벤치마크 문제에 대해서 실험을 하였고, 표준 GP 연산자와 비교하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.43-50
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• 2005

In this paper, quaternary logic gates using Down literal circuit(DLC) has been designed, and then synchronous Quaternary un/down counter using those gates has been proposed The proposed counter consists of T-type quaternary flip flop and 1-of-2 threshold-t MUX, and T-type quaternary flip flop consists of D-type quaternary flip flop and quaternary logic gates(modulo-4 addition gates, Quaternary inverter, identity cell, 1-of-4 MUX). The simulation result of this counter show delay time of 10[ns] and power consumption of 8.48[mW]. Also, assigning the designed counter to MVL(Multiple-valued Logic) circuit, it has advantages of the reduced interconnection and chip area as well as easy expansion of digit.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.4
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• pp.75-81
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• 2013

We presents a novel (2, 2) secret sharing (SS) scheme for all grayscale images. Generally, a secret image is distribute more than two shadow images, which are dealt out among participants. In order to find out secret image, participants print shadow images to transparent papers. Then, a secret image will appear as stacking transparent papers. The secret sharing scheme in this paper distribute secret image into natural grayscale images using multiplexer and data hiding scheme. After then, two participant have two shadow images respectively. The merit of the proposed scheme is that shadow images have small loss in aspect of the quality with steganographic features. Therefore, the proposed secret sharing scheme in this paper is not easily detected by attackers. The experiment result verified that the proposed scheme, obviously outperforms previous SS schemes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.675-676
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• 2013

This paper presents a design method for multiple-output combinational digital logic systems using time domain based on multiplexing and common multi-terminal extension decision diagrams. The common multi-terminal extension decision diagrams represents extension valued multiple-output functions, while time domain based on multiplexing systems transmit several signals on a single lines. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams, that is the common binary decision diagrams and common multi-terminal extension decision diagrams.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.3
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• pp.119-123
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• 2006

The orthogonal frequency-division multiplexing (OFDM) technique is well known to be robust against the frequency-selective fading in wireless channels. It is due to the exploitation of a guard interval that is inserted at beginning of each OFDM symbol. Based on the conventional OFDM and a polyphase filtered orthogonal frequency division multiplexing (PF-OFDM) technique, we developed an adaptive beamforming algorithm for antenna arrays. The proposed algorithm would lead to an efficient use of channel, since it is possible to eliminate a guard interval and also easily suppress interchannel interference at the same time. In this paper, a series of computer simulations have been provided to show the performance of the proposed system.