• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.135-144
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• 2003

This work proposes on-chip full CMOS current and voltage references for high-speed mixed-mode circuits. The proposed current reference circuit uses a digital-domain calibration method instead of a conventional analog calibration to obtain accurate current values. The proposed voltage reference employs internal reference voltage drivers to minimize the high-frequency noise from the output stages of high-speed mixed-mode circuits. The reference voltage drivers adopt low power op amps and small- sized on-chip capacitors for low power consumption and small chip area. The proposed references are designed, laid out, and fabricated in a 0.18 um n-well CMOS process and the active chip area is 250 um x 200 um. The measured results show the reference circuits have the power supply variation of 2.59 %/V and the temperature coefficient of 48 ppm/$^{\circ}C$ E.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.96-96
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• 2012

복합분자펌프는 기존의 터보분자펌프 turbine blade에 spiral grooved를 추가하여 초고진공(10-8Pa)에서 저진공(330Pa)까지 넓은 압력범위에서 사용할 수 있고 이 펌프를 사용함으로서 완전 oil free한 진공시스템을 만들 수 있는 특징을 가지고 있다. 특히, 회전체를 비접촉으로 지지하는 자기베어링 방식을 적용함으로써, 진동은 극히 작고 베어링수명은 길면서 중저진공에 대한 배기속도가 크고 임의의 방향으로 접속이 가능하여 반도체 및 디스플레이 제조 공정과 같은 첨단산업의 다양한 분야에 쉽게 적용되고 있으며, 그 적용 분야와 시장은 계속 성장하고 있다. 고 진공과 배기 속도의 달성을 위해서, 고속으로 이동하는 격면과 기체분자를 충돌시켜, 기체 분자를 원하는 방향으로 유도하는 작동원리를 가지고 있다. 특히 공기분자의 밀도가 매우 낮은 희박가스 상태에서 고속 회전하는 blade로 공기분자를 쳐내면서 작동됨으로써 날개의 상하 압력차에 의한 공기력보다도 날개의 고속회전이 매우 중요시되고 압력으로는 10-1 Pa 이하의 분자영역에서 그 성능을 최고로 발휘할 수 있다. 이러한 복합 펌프의 주요 장점은 다음과 같다. 1. 10-8 Pa (10-10 torr) ~ 10 Pa (1 torr) 까지 넓은 영역에서 배기가 가능하다. 2. 탄화수계의 대하여 높은 압축특성을 가지고 있고, 윤활유를 사용하지 않으므로 얻을 수 있는 진공상태가 고청정하다(oil free). 3. 정밀 5축제어 자기베어링으로 완전히 부상하여 회전함으로서 마모가 없고 진동이 최소화하였을 뿐 만 아니라, 또한 운전음도 거의 없다. 4. 설치조건에 제한이 없고 고장이 거의 없다. 특히 복합분자펌프는 탄화수소화합물이 없는 진공을 생성시키면서 구성요소가 간단한 반면 폭넓은 진공대역을 충족하기 때문에 산업계와 연구계의 주요 첨단 분야에서 광범위하게 사용되고 있으며, 최근 반도체 및 디스플레이, 바이오엔지니어링 등의 발전으로 적용분야가 넓어지고 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.17-22
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• 2006

CMOS LC VCO with fast response adaptive frequency calibration (AFC) technique for IEEE 802.11a/b/g WLANs is designed in 1.8V $0.18{\mu}m$ CMOS process. The possible operation is verified for 5.8GHz band, 5.2GHz band, and 2.4GHz band using the switchable L-C resonators. To linearize its frequency-voltage gain (Kvco), optimized multiple MOS varactor biasing tecknique is used. In order to operate in each band frequency range with reduced VCO gain, 4-bit digitally controlled switched- capacitor bank is used and a wide-range digital logic quadricorrelator (WDLQ) is implemented for fast frequency detector.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.15-22
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• 2005

This paper proposes an efficient structure which is able to perform self-detection and self-repair for faults in a digital system by imitating the structure of living beings. The self-repair system is composed of artificial cells, which have homogeneous structures in the two-dimension, and spare cells. An artificial cell is composed of a logic block based on multiplexers, and a genome block, which controls the logic block. The cell is designed using DCVSL (differential cascode voltage switch logic) structure to self-detect faults. If a fault occurs in an artificial cell, it is self-detected by the DCVSL. Then the artificial cells which belong to the column are disabled and reconfigured using both neighbour cells and spare cells to be repaired. A self-repairable 2-bit up/down counter has been fabricated using Hynix $0.35{\mu}m$ technology with $1.14{\times}0.99mm^2$ core area and verified through the circuit simulation and chip test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.2
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• pp.111-116
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• 2003

In this paper, a CMOS baseband analog receiver for wireless home network is discussed. It is composed of a Gilbert type mixer, an Elliptic 6th order 1ow pass filter, and a 6-bit A/D converter. The main role of the mixer is generating a mixed analog signal between the 200MHz output signal of CMOS RF stage and the 199MHz local oscillator. After the undesired high frequency component of the mixed signal comes out. Finally, the analog signal is converted into digital code at the 6-bit A/D converter, The proposed receiver is fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly 5-metal CMOS technology, and the chip area is 200${\mu}{\textrm}{m}$ X1400${\mu}{\textrm}{m}$. the receiver consumes 130㎽ at 2.5V power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.68-73
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• 2009

This paper presents an easily modifiable structure of a serial peripheral interface (SPI) that is suitable for efficient testing of CMOS RF integrated circuits. The proposed SPI Is designed so that the address size and the accompanying software can be easily adjusted and modified according to the requirements and complexity of RF IC's under development. The hardware architecture and software algorithm to achieve the flexibility are described. The proposed SPI is fabricated in $0.13{\mu}m$ CMOS and successfully verified experimentally with a 2.7GHz fractional-N delta-sigma frequency synthesizer as a device under test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.7-13
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• 2010

A compact phase interpolator (PI) based spread spectrum clock generator (SSCG) for electromagnetic interference (EMI) reduction is presented. The proposed SSCG utilizes a digitally controlled phase interpolation technique to achieve triangular frequency modulation with less design complexity and small power and area overhead. The novel SSCG can generate the system clock with a programmable center-spread spectrum range of up to +/- 2 % at 200 MHz, while maintaining the clock duty cycle ratio without distortions. The PI-based SSCG has been designed and evaluated in 0.18-um 1.8-V CMOS technology, which consumes about 5.0 mW at 200MHz and occupies a chip size of $0.092mm^2$ including a DLL.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.43-51
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• 2013

This paper presents a design and implementation of a low power switched-capacitor 3rd-order delta-sigma modulator for a digital hearing-aid application. The power consumption is reduced by minimizing the output swing of integrators through optimizing the coefficients of modulator architecture and using class-AB output operational amplifiers. The modulator was implemented in a 130nm CMOS technology, and measured to have 79dB of SNR(Signal-to-Noise Ratio) in the signal bandwidth between 100Hz and 10kHz with an oversampling ratio of 160. The power consumption was $60{\mu}W$ from 1.2V power supply and the modulator core occupied $0.53mm{\times}0.53mm$.

• Journal of IKEEE
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• v.15 no.1
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• pp.29-36
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC is employed to overcome the problems of dithering scheme. A 2.4GHz LC-based DCO has been designed in a $0.13{\mu}m$ CMOS process with an enhanced frequency resolution for wireless local area network applications. It has a frequency tuning range of 900MHz and a resolution of 58.8Hz. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The designed DCO exhibits a phase noise of -123.8dBc/Hz at 1MHz frequency offset. The DCO core consumes 4.2mA from 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.42-50
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• 2006

Owing to the development of semiconductor processing technology, high density complex circuits can be integrated in a System-on-Chip (SoC). However, increasing energy consumption becomes one of the most important limiting factors. Power estimation at the early stage of design is essential, since design changes at lower levels may significantly lengthen the design period and increase the cost. In this paper, logic level circuits ire levelized and several levels are selected to build power model tables for efficient power estimation. The proposed techniques are applied to a set of ISCAS'85 benchmark circuits to illustrate their effectiveness. Experimental results show that significant improvement in estimation accuracy and slight improvement in efficiency are achieved when compared to those of a well-known existing method. The average estimation error has been reduced from $9.49\%\;to\;3.84\%$.