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New Model-based IP-Level Power Estimation Techniques for Digital Circuits  

Lee, Chang-Hee (School of Electrical and Computer Engineering Hanyang University)
Shin, Hyun-Chul (School of Electrical and Computer Engineering Hanyang University)
Kim, Kyung-Ho (Telecom R&D Center, Telecommunication Networks Samsung Electronics)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.2, 2006 , pp. 42-50 More about this Journal
Abstract
Owing to the development of semiconductor processing technology, high density complex circuits can be integrated in a System-on-Chip (SoC). However, increasing energy consumption becomes one of the most important limiting factors. Power estimation at the early stage of design is essential, since design changes at lower levels may significantly lengthen the design period and increase the cost. In this paper, logic level circuits ire levelized and several levels are selected to build power model tables for efficient power estimation. The proposed techniques are applied to a set of ISCAS'85 benchmark circuits to illustrate their effectiveness. Experimental results show that significant improvement in estimation accuracy and slight improvement in efficiency are achieved when compared to those of a well-known existing method. The average estimation error has been reduced from $9.49\%\;to\;3.84\%$.
Keywords
Low-power; Power estimation; Power modeling;
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