Browse > Article

Design for Self-Repair Systm by Embeded Self-Detection Circuit  

Seo Jung-Il (Dept of Semiconductor Eng., Chungbuk National University)
Seong Nak-Hun (LG.PHILIPS LCD Co.)
Oh Taik-Jin (PIXELPLUS Co.)
Yang Hyun-Mo (Dept of Semiconductor Eng., Chungbuk National University)
Choi Ho-Yong (School of Electrical and Computer Eng. Chungbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.5, 2005 , pp. 15-22 More about this Journal
Abstract
This paper proposes an efficient structure which is able to perform self-detection and self-repair for faults in a digital system by imitating the structure of living beings. The self-repair system is composed of artificial cells, which have homogeneous structures in the two-dimension, and spare cells. An artificial cell is composed of a logic block based on multiplexers, and a genome block, which controls the logic block. The cell is designed using DCVSL (differential cascode voltage switch logic) structure to self-detect faults. If a fault occurs in an artificial cell, it is self-detected by the DCVSL. Then the artificial cells which belong to the column are disabled and reconfigured using both neighbour cells and spare cells to be repaired. A self-repairable 2-bit up/down counter has been fabricated using Hynix $0.35{\mu}m$ technology with $1.14{\times}0.99mm^2$ core area and verified through the circuit simulation and chip test.
Keywords
self-detection; self-repair; artificial cell; spare cell; DCVSL;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 V. Shen and F. Shen, 'Requirements specification and analysis of fault tolerant digital systems,' IEEE Trans. on Man and Cybernetics, Part A, vol. 32, no. 1, pp. 149-159, Jan. 2002   DOI   ScienceOn
2 H. Fahmy, S. Ghoneim and A. Pacha, 'Fault tolerant communication with partitioned dimension-order routers with complex faults,' in Proc. of 15th International Conference on Information Networking, pp. 361-366, Jan. 2001   DOI
3 M. Yen, W. Fuchs, and J. Abraham, 'Designing for concurrent error detection in VLSI: Application to a microprogram control unit,' IEEE J. Solid State Circuits, vol. 22, no. 4, pp. 595-605, Apr. 1987   DOI
4 B. Yang and Y. Chen, 'Space and Time Efficient BDD Construction via Working Set controller,' in Proc. of ASPDAC '98, pp. 423-432, Feb. 1998   DOI
5 D. Mange, 'Embryonics: A new methodology for designing FPGA with self-repair and self-replicationing,' IEEE Trans. on VLSI Systems, vol. 6, no 3, pp. 387-399, Sept. 1998   DOI   ScienceOn
6 C. Ortega-Sanchez and A. Tyrell, 'Design of a basic cell to construct embryonic array,' in Proc. of IEEE Computers and Digital Techniques, vol. 145, no. 3, pp. 242-248, May 1998   DOI
7 L. Prodan, G. Tempesti, D. Mange, and A. Stauffer, 'Embryonics: Artificial cells driven by artificial DNA,' in Proc. of 4th International Conference ICES, Lecture Notes in Computer Science, pp. 100-111, May 2001   DOI
8 M. Rabaey, Digital Integrated Circuits, Prentice-Hall Inc., pp. 522-543, 1996
9 D. Bradley and A. Tyrrell. 'Hardware Immune System for Benchmark State Machine Error Detection,' IEEE Trans. on Evolutionary Computation, vol. 1, pp.813-818, May 2002   DOI
10 D. Bradley and A. Tyrrell. 'Immunotronics: Novel finite state machine architectures with built-in self-test using self-nonself differentiation,' IEEE Trans. on Evolutionary Computation, vol. 6, no.3, pp. 222-238, June 2002   DOI   ScienceOn