• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.69-70
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• 2015

본 논문에서는 GaN HEMT를 이용하여 동기 벅 컨버터 구동 시 기생 커패시턴스, 기생 인덕턴스 등에 의해 발생하는 노이즈를 분석한다. 노이즈 분석을 통해, dv/dt의 크기에 따라 발생하는 전류가 각 게이트-소스 단 전압 노이즈의 원인이 되는 것을 확인하였다. 노이즈의 원인인 dv/dt를 줄이기 위한 외부 회로를 제안하여 GaN HEMT의 안정적인 동작을 실험을 통해 검증한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.194-200
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• 2012

In this paper, we proposed a SPICE model of high-voltage insulated gate bipolar transistor(IGBT). The proposed model consists of two sub-devices, a MOSFET and a BJT. Basic I-V characteristics and their temperature dependency were realized by adjusting various parameters of the MOSFET and the BJT. To model nonlinear parasitic capacitances such as a reverse-transfer capacitance, multiple junction diodes, ideal voltage and current amplifiers, a voltage-controlled resistor, and passive devices were added in the model. The accuracy of the proposed model was verified by comparing the simulation results with the experimental results of a 1200V trench gate IGBT.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.15-19
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• 2016

The gate bias dependence of kink phenomenon with a large deviation from the resistance circle in Smith chart is observed in the frequency response of $S_{11}$-parameter for large multi-finger RF MOSFETs. For the first time, this bias dependence is analyzed by measuring magnitude and phase of $S_{11}$-parameter, input resistance and input capacitance. As a result, $V_{gs}$ dependent $S_{11}$-parameter is largely changed by the magnitude of input capacitance as well as dominant pole and zero frequencies of input resistance. At $V_{gs}=0V$, the kink phenomenon occurs in the high frequency region because of very small phase difference of $S_{11}$-parameter and high pole frequency of input resistance. However, the kink phenomenon at higher $V_{gs}$ is generated in the low frequency region owing to large phase difference and low pole frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.56-61
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• 2015

Ideal and stretch-out C-V curve were shown at high frequency using SiGe p-FinFET simulation. Average interface trap density can be extracted by the difference of voltage axis on ideal and stretch-out C-V curve. Also, interface trap density(Dit) was extracted by Terman's method that uses the same stretch-out of C-V curve with interface trap characteristic, and average interface trap density was calculated at same energy level. Comparing the average interface trap density, which was found by method using difference of voltage, with Terman's method, it was verified that the two methods almost had the same average interface trap density.

• 전자공학회논문지 IE
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• v.44 no.2
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• pp.1-7
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• 2007

The increasing high frequency capabilities of CMOS have resulted in increased RF and analog design in CMOS. Design of RF and analog circuits depends critically on device S-parameter characteristics, magnitude of real and imaginary components and their behavior as a function of frequency. Utilization of scaled high performance CMOS technologies poses challenges as concerns for reliability degradation mechanisms increase. It is important to understand and quantify the effects of the reliability degradation mechanisms on the S-parameters and in turn on small signal model parameters. Various physical effects influencing small-signal parameters, especially the transconductance and capacitances and their degradation dependence, are discussed in detail. The measured S-parameters of H-gate and T-gate devices in a frequency range from 0.5GHz to 40GHz. All intrinsic and extrinsic parameters are extracted from S-parameters measurements at a single bias point in saturation. In this paper we discuss the analysis of the small signal equivalent circuits of RF SOI MOSFET's verificated for the purpose of exacting the change of parameter of small signal equivalent model followed by device flame.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.72-79
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• 2003

Classical designs of optical transimpedance preamplifier for p-i-n photodiode receiver circuits generally employ common source transimpedance input stages. In this paper, we explore the design of a class of current-mode optical transimpedance preamplifier based upon common gate input stages. A feature of current-mode optical transimpedance preamplifier is high gain and high bandwidth. The bandwidth of the transimpedance preamplifier can also be increased by the capacitive peaking technique. In this paper we included the development and application of a circuit analysis technique based on the minimum noise. We develop a general formulation of the technique, illustrate its use on a number of circuit examples, and apply it to the design and optimization of the low-noise transimpedance amplifier. Using the noise minimization method and the capacitive peaking technique we designed a transimpedance preamplifier with low noise, high-speed current-mode transimpedance preamplifier with a 1.57GHz bandwidth, and a 2.34K transimpedance gain, a 470nA input noise current. The proposed preamplifier consumes 16.84mW from a 3.3V power supply.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.54-61
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• 1999

We suggested a macro medel for MOS transistors, which incorporates the distributed substrate resistance by using a method which utilizes external diodes on SPICE MOS model. By fitting the simulated s-parameters to the measures ones, we obtained a model set for the W=200TEX>$\mu\textrm{m}$ and L=0.8TEX>$\mu\textrm{m}$ NMOS transistor, and also analyzed the effects of distributed substrate resistance in the RF range. By comparing the physical parameters calculated from simulated s-parameters such as ac resistances and capacitances with the measured ones, we confirmed the validity of the simulation results. For the frequencies below 10GHz, it seems appropriated to use a simple macro model which utilizes the existing SPICE MOS model with junction diodes, after including one lumped resistor each for gate and substrate nodes.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.49-53
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• 2016

A new large-signal model including the voltage-dependent extrinsic gate capacitance for RF channel distribution effect is developed for a high resistivity(HR) silicon-on-insulator(SOI) RF accumulation-mode MOS varactor. The data of voltage-dependent parameters are extracted by using accurate S-parameter optimization, and empirical model equations are constructed by data fitting process. The RF accuracy of this new model is validated by observing excellent agreements between modeled and measured Y11-parameter data in the wide voltage range up to 20 GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.777-779
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• 2003

In this paper, we have investigated Characteristics of C-V for Double gate MOSFET with main gate and side gate. DG MOSFET has the main gate length of 50nm and the side gate length of 70nm. We have investigated characteristics of C-V and main gate voltage is changed from -5V to ＋5V. Also we have investigated characteristics of C-V for DG MOSFET when the side gate length is changed from 40nm to 90nm. As the side gate length is reduced, the transconductance is increased and the capacitance is reduced. When the side gate voltage is 3V, we know that C-V curves are bending at near the main gate voltage of 1.8V. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.28-29
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• 2017

기존의 위상천이 풀 브리지 DC/DC 컨버터의 경우 변압기의 누설 인덕턴스와 2차 측 정류 다이오드의 기생 출력 커패시턴스 사이의 공진으로 인하여 정류 다이오드 양단에 큰 공진 전압이 발생하며, 이는 소자의 신뢰성 저하 및 시스템의 전력 변환 효율을 감소시킨다. 반면 LLC 공진형 컨버터는 2차 측에서 발생되는 공진 에너지가 출력 커패시터로 흡수되지만 경 부하시에 높은 스위칭 주파수로 인하여 효율이 저감되며, 출력 전압을 제어하기 위해 추가적인 부하저항이 요구된다. 따라서 최근에는 LLC 공진형 컨버터로 동작시키면서도 PWM 제어를 통해 출력전압을 제어하는 방법이 연구되고 있으나, 새로운 게이트 구동 방식을 위해 DSP 제어를 사용하고 있다. 따라서 본 논문에서는 산업에서 많이 사용되고 있는 아날로그 IC를 통해 동일한 동작 및 성능을 구현시킬 수 있는 방법에 대하여 제안한다. 본 논문에서는 제안된 방식의 타당성을 검증하기 위하여 이론적으로 분석하며, 6.6kW급 시작품을 제작하여 제안방식의 타당성을 검증하였다.