• IEIE Transactions on Smart Processing and Computing
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• v.5 no.2
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• pp.71-76
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• 2016

A controller area network (CAN) receiver measures differential voltage on a bus to determine the bus level. Since 3.3V transceivers generate the same differential voltage as 5V transceivers (usually ${\geq}1.5V$), all transceivers on the bus (regardless of supply voltage) can decipher the message. In fact, the other transceivers cannot even determine or show that there is anything different about the differential voltage levels. A new CMOS RC oscillator insensitive supply voltage for clock generation in a CAN transceiver was fabricated and tested to compensate for this drawback in CAN communication. The system consists of a symmetrical circuit for voltage and current switches, two capacitors, two comparators, and an RS flip-flop. The operational principle is similar to a bistable multivibrator but the oscillation frequency can also be controlled via a bias current and reference voltage. The chip test experimental results show that oscillation frequency and power dissipation are 500 kHz and 5.48 mW, respectively at a supply voltage of 3.3 V. The chip, chip area is $0.021mm^2$, is fabricated with $0.18{\mu}m$ CMOS technology from SK hynix.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.12
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• pp.1236-1242
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• 2014

In this work, a D-band VCO(Voltage Controlled Oscillator) has been developed in a 65-nm CMOS technology. The circuit was designed based on push-push mechanism. The output oscillation frequency of the fabricated VCO varied from 152.7 GHz to 165.8 GHz, and the measured output power was from -17.3 dBm to -8.7 dBm. A phase noise of -90.9 dBc/Hz is achieved at 10 MHz offset. The chip size of the circuit is $470{\mu}m{\times}360{\mu}m$ including the probing pads.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.82-88
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• 2014

An available capacitance increasing phase-locked loop(PLL) with two voltage controlled oscillator gains has been proposed. In this paper, the available capacitance of loop filter is increased by using two positive/negative gains of voltage controlled oscillator (VCO). It results in 1/10 reduction in the size of loop filter capacitor. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and a locking time of conventional PLL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.268-272
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• 2001

In this thesis, PLVCO(Phase Locked Voltage Controlled Oscillator) using 24.42 GHz voltage controlled hair-pin resonator oscillator, Sequency divider, buffer amplifier, -10 dB directional coupler and phase detector is designed and fabricated for B-WLL. The PLVCO shows the oscillator output power of 16.5 dBm at 24.42 GHz, and phase noise of -76.3 dBc/Hz at 1001:Hz offset, -72.8dBc/Hz at 10 kHz offset from fundamental frequency.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.293-297
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• 2009

In this thesis, design of a VCO(Voltage controlled Oscillator) with a novel tuning mechanism is presented for the Radar system. This circuit, the 9.5 GHz oscillator is designed and implemented by restructuring microstrip resonator to raise Q value and to require a wide frequency tuning range. This product is fabricated on 2.6 Teflon substrate and device is NE722S01. In this paper, The new microstrip resonator VCO is proposed to achieve the characteristic of a wide frequency tuning range. This microstrip resonator VCO shows the phase noise characteristic of -108.3 dBc/Hz at 1 MHz offset from the fundamental frequency, the output power of 5.7 dBm and the second harmonic suppression of -38 dBc for the VCO are obtained. The manufacture VCO shows a frequency tuning range of 193.8 MHz. The proposed micro trip resonator VCO can be used for X-band Radar System with required tuning range.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.2
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• pp.219-225
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• 1998

A voltage controlled oscillator for the local oscillator in 380 MHz TRS handset is designed and fabricated. To improve the phase noise characteristics, the NEC's 2SC4226 transistor with NF=1.2 at 1 GHz and Toshiba's 1SV229 varactor diode with Q=70 are used. And an inductor of VCO is realized by microstrip line. At the bias condition of 5 V and 10 mA, the output power and phase noise in the operating frequency range of 357∼387 MHz are above 3.7 dBm and 111 dBc/Hz at 12.5KHz offset from the carrier, respectively. And FM sensitivity deviation are within ±0.4 KHz. This VCO is well suited for TRS handset.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.275-278
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• 2008

In this paper, I propose the full CMOS FLL(frequency locked loop) circuit. The proposed FLL circuit has a simple structure which contains a FVC(frequency-to-voltage converter), an operational amplifier and a VCO(voltage controlled oscillator). The operation of FLL circuit is based on frequency comparison by the two FVC circuit blocks. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. The circuit is designed by 0.35${\mu}m$ process and simulation carried out with HSPICE. Simulation results are shown to illustrate the performance of the proposed FLL circuit.

• ETRI Journal
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• v.34 no.4
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• pp.518-526
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• 2012

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.699-702
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• 2012

본 논문에서는 WCDMA(Wide Code Division Multiple Access) 시스템 사양을 만족시키는 주파수 합성기 블록 중 위상잡음 및 전력소모의 최적 설계가 필요한 LC-VCO(voltage controlled oscillator)의 설계를 제안 하였다. 최적 설계를 위한 핵심내용은 LC-tank의 손실성분을 보상하는 MOS트랜지스터의 전달컨덕턴스와 인덕턴스 평면에 여유이득라인과 튜닝 범위 라인을 그어 설계 가능한 영역 내에서 위상잡음이 최소가 되는 인덕턴스 값을 구하고 선택하는 것이다. 제안한 최적 설계방법에 의해 진행된 LC-VCO의 시뮬레이션 결과 위상잡음 특성은 1MHz옵셋에서 -113dBc/Hz였다.