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Digitally controlled phase-locked loop with tracking analog-to-digital converter  

Cha, Soo-Ho (Department of Electronics and Computer Engineering, Hanyang University)
Yoo, Chang-Sik (Department of Electronics and Computer Engineering, Hanyang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.9, 2005 , pp. 35-40 More about this Journal
Abstract
A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.
Keywords
Phase-locked loop; Tracking ADC; DAC;
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