• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.14-15
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• 2006

Application of the parallel Build-up is increasing continuously. This report presents about the PCB Build-up technology since 2000. Among the parallel build-up technologies, PALAP application - after making the via, filling the via with electric conductive paste, then expose to make wiring pattern and put them by layer without any glue or middle - is actively developing, especially DENSO company.

• Korean Journal of Metals and Materials
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• v.48 no.6
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• pp.557-564
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• 2010

Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

• Clean Technology
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• v.17 no.2
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• pp.103-109
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• 2011

The process optimization was carried out to improve the throwing power (TP) and the thickness uniformity of the electroless copper (Cu) plating, which plays a seed layer for the subsequent electroplating. The DOE (design of experiment) was employed to screen key factors out of all available operation parameters to influence the TP and thickness uniformity the most. It turned out that higher Cu ion concentration and lower plating temperature are advantageous to accomplish uniform via filling and they are accounted for based on the surface reactivity. To visualize what occurred experimentally and evaluate the phenomena qualitatively, the kinetic Monte Carlo (MC) simulation was introduced. The combination of neatly designed experiments by DOE and supporting theoretical simulation is believed to be inspiring in solving similar kinds of problems in the relevant field.

• Journal of the Korean institute of surface engineering
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• v.47 no.2
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• pp.68-74
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• 2014

The seed step-coverage enhancement process (SSEP) using Pd/Cu/PVP colloids was investigated for the filling of through silicon via (TSV) without void. TEM analysis showed that the Pd/Cu nano-particles were well dispersed in aqueous solution with the average diameter of 6.18 nm. This Pd/Cu nano-particles were uniformly deposited on the substrate of Si/$SiO_2$/Ti wafer using electrophoresis with the high frequency Alternating Current (AC). After electroless Cu deposition on the substrate treated with Pd/Cu/PVP colloids, the adhesive property between deposited Cu layer and substrate was evaluated. The Cu deposit obtained by SSEP with Pd/Cu/PVP colloids showed superior adhesion property to that on Pd ion catalyst-treated substrate. Finally, by implementing the SSEP using Pd/Cu/PVP colloids, we achieved 700% improvement of step coverage of Cu seed layer compared to PVD process, resulting in void-free filling in high aspect ratio TSV.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2020.11a
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• pp.90-91
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• 2020

Utilization of upgraded fine fly ash in cement-based materials has been proved by many researchers as an effective method to improve compressive strength of cement based materials at early ages. The addition of fine fly ash has introduced dilution effect, enhanced pozzolanic reaction effect, nucleation effect and physical filling effect into cement-fly ash system. In this study, an integrated reaction model is adpoted to quantify the contributions from cement hydration and pozzolanic reaction to compressive strength. A modified model related to the physical filling effect is utilized to calculate the compressive strength increment considering the gradual dissolution of fly ash particles. Via combination of these two parts, a numerical model has been proposed to predict the compressive strength development of fine fly ash mortar considering fly ash fineness. The reliability of the model is validated through good agreement with the experimental results from previous articles.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.76-81
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• 2011

A new via cutting structure in 2-layer DRAM package substrate has been fabricated to lower its power distribution network(PDN) impedance. In new structure, part of the via is cut off vertically and its remaining part is designed to connect directly with the bonding pad on the package substrate. These via structure and substrate design not only provide high routing density but also improve the PDN impedance by shortening effectively the path from bonding pad to VSSQ plane. An additional process is not necessary to fabricate the via cutting structure because its structure is completed at the same time during a process of window area formation. Also, burr occurrence is minimized by filling the via-hole inside with a solder resist. 3-dimensional electromagnetic field simulation and S-parameter measurement are carried out in order to validate the effects of via cutting structure and VDDQ/VSSQ placement on the PDN impedance. New DRAM package substrate has a superior PDN impedance with a wide frequency range. This result shows that via cutting structure and power/ground placement are effective in reducing the PDN impedance.

• Publications of The Korean Astronomical Society
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• v.7 no.1
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• pp.19-23
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• 1992

We investigated the "tilting" of the Universe, i.e., a non-Doppler origin of the dipole moment of the cosmic background radiation (CBR). Superhorizon-sized isocurvature, rotational and true vacuum bubble perturbations are considered. We show that the more natural way of the "tilting" the Universe is via the true vacuum bubble perturbation. Nevertheless, due to the small filling fraction of the bubbles of viable extended inflationary models, we find that the probability of the real occurrence in the Universe is quite insignificant.

• Proceedings of the KWS Conference
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• 2006.05a
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• pp.227-229
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• 2006

3차원 실장을 하기 위해서 딥핑 방법으로 전기적 신호를 전달할 수 있는 비아를 가진 실리콘 웨이퍼를 제작하였다. 레이저를 이용하여 실리콘 웨이퍼에 개구부가 원형에 가까운 관통 홀을 형성하였다. 관통 홀의 벽에 도금 방법으로 시드 층을 형성하였다. 관통 홀의 충전 금속은 Sn-3.5Ag-0.7Cu 솔더를 사용하였다. 딥핑 방법으로 시드 층과 솔더 사이의 확산 현상 이용하여 전기적 신호를 전달 할 수 있는 비아를 형성하였다. 비아 내부에 일부 기공과 크랙이 발견되기도 했으나 딥핑 방법을 통해서 빠른 시간 내에 비아를 가진 실리콘 웨이퍼를 제작 할 수 있었다.

• Journal of the Korean Graphic Arts Communication Society
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• v.24 no.1
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• pp.35-44
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• 2006

본 연구에서는 PCB에 진공인쇄 방식이 적용된 스크린 인쇄방법을 이용하여 Pattern 및 Hole충전의 신뢰성을 향상시킬 수 있는 기술을 적용하였다. 새로운 dry process 기술인 직접회로 인쇄 기술은 일반적으로 사용되고 있는 wet process 중 도금, 에칭, 박리 등의 공정을 줄일 수 있어 제조원가, 공정 리드타임 감소, 폐기물 감소로 환경 친화적 공정이라고 할 수 있다. 직접회로 인쇄는 진공도 100 Pa, 인쇄압력 0.45 MPa, 인쇄 속도 30 mm/sec, 인쇄각도 85도, 스크린 마스크와 기판 사이의 Gap 2 mm에서 인쇄될 때 가장 좋은 결과를 보였다. 직접회로 인쇄에 사용된 인쇄기는 일반 PCB공정에서 사용되는 동일한 형태에 진공조건을 유지시킬 수 있도록 개선하여 사용하였다.

• Journal of Electrochemical Science and Technology
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• v.8 no.2
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• pp.146-154
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• 2017

In this study, copper (II) oxide was prepared for use in a copper electroplating solution. Copper chloride powder and copper (II) oxide are widely used as raw materials for electroplating. Copper (II) oxide was synthesized in this study using a two-step chemical reaction. Herein, we developed a method for the preparation of copper (II) oxide without the use of sintering. In the first step, copper carbonate was prepared without sintering, and then copper (II) oxide was synthesized without sintering using sodium hydroxide. The optimum amount of sodium hydroxide used for this process was 120 g and the optimum reaction temperature was $120^{\circ}C$ regardless of the starting material.