• ETRI Journal
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• v.24 no.5
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• pp.391-397
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• 2002

This paper presents digital signal processor (DSP) instructions and their data processing unit (DPU) architecture for high-speed fast Fourier transforms (FFTs) in orthogonal frequency division multiplexing (OFDM) systems. The proposed instructions jointly perform new operation flows that are more efficient than the operation flow of the multiply and accumulate (MAC) instruction on which existing DSP chips heavily depend. We further propose a DPU architecture that fully supports the instructions and show that the architecture is two times faster than existing DSP chips for FFTs. We simulated the proposed model with a Verilog HDL, performed a logic synthesis using the 0.35 ${\mu}m$ standard cell library, and then verified the functions thoroughly.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.321-324
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• 2001

This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32$\times$32 bit multiplication, and was designed using verilog HDL and 0.35${\mu}{\textrm}{m}$, 3V, 4M CMOS standard cell library. Its target operating speed is 40MHz, area lower than 10000 gate counts, and 10mW/MHz of power.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.141-144
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• 2003

인터넷 사용자의 증가와 데이터 전송양이 폭발적으로 증가하면서, 네트워크에도 고속화 및 다기능화가 요구되고 있다. 또한, IPv4의 주소 부족 문제를 해결하기 위해 IPv6의 표준화가 진행 중인데, IPv4와 IPv6는 서로 다른 주소 체계를 사용하므로 상호 연동하기 위한 방안이 제공되어야 한다. 본 논문에서는 IPv4-IPv6 간 연동을 위한 메커니즘인 변환 방식과 터널링 방식에 모두 이용되고, 데이터의 고속 처리를 위해 프로토콜 듀얼 스택 중 3계층과 4계층을 하드웨어로 설계하였다. 특히, 3계층은 IP 기반의 고속 네트워크를 위해 듀얼 스택으로 구현함으로써 IPv4, IPv6 패킷을 단일 노드에서 처리할 수 있는 장점을 지닌다. 본 논문에서 제안한 네트워크 프로세서는 Verilog HDL을 이용하여 설계하였으며, 실제 네트워크 상의 패킷 정보를 볼 수 있는 Ethereal 프로그램을 이용하여 구한 테스트 벡터로 시뮬레이션 및 검증을 하였다.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2132-2135
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• 2003

본 논문에서는 고정소수점 DSP로 구현한 실시간 MP3 오디오 부호화기에 사용되는 초월함수용 하드웨어 가속기 구조를 제안한다. 구현된 하드웨어 가속기는 MP3 부호화 성능을 저하시키는 초월함수 연산오차에 강인하도록 설계되었다. 제안된 가속기의 연산오차는 Q1.23 고정소수점 출력에서 2비트, 즉 2/sup -21/ 까지의 연산오차를 가진다. LAME 부호화기[5]심리음향 모델의 SMR 오차는 테이블 보간법[4]을 사용할 경우에 비해 4dB이상 향상되었으며, 연산량은 총 4 MIPS 감소하였다. 제안한 하드웨어 가속기는 Verilog HDL로 기술되었으며, SYNOPSYS에서 0.18㎛ CMOS 표준 셀 라이브러리 공정으로 합성되었다. 합성 면적은 7514 게이트이며 초월함수 연산에 대한 동작속도는 3 사이클이다.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.353-357
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• 2014

This paper, presents an efficient hardware architecture of high performance SVC(Scalable Video Coding). This platform uses dedicated hardware architecture to improve its performance. The architecture was prototyped in Verilog HDL and synthesized using the Synopsys Design Compiler with a 65nm standard cell library. At a clock frequency of 266MHz, This platform contains 2,500,000 logic gates and 750,000 memory gates. The performance of the platform is indicated by 30 frames/s of the SVC encoder Full HD($1920{\times}1080$), HD($1280{\times}720$), and D1($720{\times}480$) at 266MHz.

• Journal of IKEEE
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• v.18 no.4
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• pp.630-635
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• 2014

In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.1
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• pp.19-26
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• 2011

In this paper, we designed Interpolation FIR(Finite Impulse Response) filter and 1-bit SDM(Sigma- Delta Modulator) for small digital audio speaker, which has low power consumption and high output characteristics. In order to achieve high linearity and low distortion performance of the systems, we adopt Type I Chevychev FIR filter which has equiripple characteristics in the pass band and proposed high efficient FIR filter structure. SDM is the most efficient modulation technique among the noise shaping techniques. In this paper, we implemented SDM using CIFB(Cascade of Intergrators, Feed-Back) which is generally used in DAC of small digital audio speakers. The proposed SDM structure can achieve high SNR, high-efficiency characteristics and low power consumption in mobile devices. Also considering manufacture of SoC(System on Chip), we performed simulation with Matlab and Verilog HDL to obtain optimal number of operational bits and verified a good experimental results.

• Journal of Korea Multimedia Society
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• v.5 no.2
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• pp.206-214
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• 2002

In this paper, it is designed and verified the baseband system that performs various protocol functions of specification of the Bluetooth system. In order to verify the developed circuits, various baseband functions are tested by using the ModelSim simulator. The developed circuits operate at 4MHz main clock. Test suite includes hap selection function, generation of the sync word, error correction(1/3 rate FEC, 2/3 rate FEC), HEC generation/checking, CRC generation/checking, data whitening/dewhitening and packet trans/reception procedure. etc. As a result of the simulation, it is verified that the developed baseband system conform to the specification of the Bluetooth system.

• Annual Conference of KIPS
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• 2005.05a
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• pp.1737-1740
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• 2005

MP3 음악과 같은 오디오 컨텐츠의 저작권 보호를 위한 다양한 오디오 워터마킹 기법이 활발히 연구되고 있다. 본 논문에서는 XUEYAO LI[1]가 제안한 방법을 기반으로 VLSI H/W구조를 제안하며 이를 Verilog HDL을 이용하여 설계 및 시뮬레이션을 수행하였다. 본 논문에서 사용한 워터마크 삽입 기법은 시각적 식별성이 뛰어난 이진 이미지를 기반으로 의사 랜덤 수열을 생성하여 웨이브릿 영역에서의 워터마크를 삽입하는 기법이다. H/W 설계의 복잡성을 줄이기 위해 워터마크 삽입 강도를 스케일링 하는 기법을 생략하였으나 Matlab을 이용한 알고리즘 시뮬레이션 결과 워터마크 삽입 신호의 음질에 거의 영향을 주지 않으며 몇몇 알려진 워터마크 공격에도 강인성을 보였다.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.5 no.2
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• pp.102-107
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• 2005

This paper presents the comparison and performance analysis for CPL and CMOS based designs. We have developed the Verilog-HDL codes for the proposed designs and simulated them using ModelSim for verifying the logical correctness and the timing properties of the proposed designs. The proposed designs are then analyzed at the layout level using LASI. The layouts of the proposed designs are simulated in Winspice for timing and power characteristics. The result shows that the new circuits presented consistently consume less power than the conventional design of the same circuits. It can also be seen that these circuits have the lesser propagation delay and thus higher speed than the conventional designs.