IEIE Transactions on Smart Processing and Computing

The Institute of Electronics and Information Engineers (대한전자공학회)
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High Performance and FPGA Implementation of Scalable Video Encoder

  • Received : 2014.02.20
  • Accepted : 2014.08.28
  • Published : 2014.12.31
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Abstract

This paper, presents an efficient hardware architecture of high performance SVC(Scalable Video Coding). This platform uses dedicated hardware architecture to improve its performance. The architecture was prototyped in Verilog HDL and synthesized using the Synopsys Design Compiler with a 65nm standard cell library. At a clock frequency of 266MHz, This platform contains 2,500,000 logic gates and 750,000 memory gates. The performance of the platform is indicated by 30 frames/s of the SVC encoder Full HD($1920{\times}1080$), HD($1280{\times}720$), and D1($720{\times}480$) at 266MHz.

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References

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Cited by

  1. Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders pp.1861-8219, 2017, https://doi.org/10.1007/s11554-017-0729-9