• Journal of the Korea Society for Simulation
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• v.23 no.3
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• pp.27-32
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• 2014

In this paper, We are going to propose the novel structure with improved behavior than the conventional vertical structure for VLSI CMOS circuits. For this, the proposed structure is the moat shape for STI. We want to analysis the characteristics of simulations about the electron concentration distribution, oxide layer shape of hot electron stress, potential flux and electric field flux, electric field fo themal damage and current-voltage characteristics in devices. Physically based models are the ambient and stress bias conditions of TCAD tool. As a analysis results, shallow trench structure were trended to be electric functions of passive as device dimensions shrink. The electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage, are decreased the stress effects of active region. The fabricated device of based on analysis results data were the almost same characteristics of simulation results data.

• Current Applied Physics
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• v.18 no.11
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• pp.1447-1450
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• 2018

The electron spin resonance (ESR) detects point defect of the In-Ga-Zn oxide (IGZO) like singly ionized oxygen vacancies and excess oxygen, and get spin density as a parameter of defect state. So, we demonstrated the spin density measurement of the IGZO film with various deposition conditions and it has linear relationship. Moreover, we matched the spin density with the total BTS and the threshold voltage ($V_{th}$) distribution of the IGZO thin film transistors. The total BTS ${\Delta}V_{th}$ and the $V_{th}$ distribution were degraded due to the spin density increases. The spin density is the useful indicator to predict $V_{th}$ instability of IGZO TFTs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.401-406
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• 2015

The change of subthreshold swing for channel length of asymmetric double gate(DG) MOSFET has been analyzed. The subthreshold swing is the important factor to determine digital chracteristics of transistor and is degraded with reduction of channel. The subthreshold swing for channel length of the DGMOSFET developed to solve this problem is investigated for channel thickness, oxide thickness, top and bottom gate voltage and doping concentration. Especially the subthreshold swing for asymmetric DGMOSFET to be able to be fabricated with different top and bottom gate structure is investigated in detail for bottom gate voltage and bottom oxide thickness. To obtain the analytical subthreshold swing, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. As a result, subthreshold swing is sensitively changed according to top and bottom gate voltage, channel doping concentration and channel dimension.

• Journal of the Korean Ceramic Society
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• v.39 no.1
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• pp.92-98
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• 2002

To investigate the electrode structural effect on the ferroelectric electron emission, the electric field distribution in a 2-dimensional structure was calculated as a function of upper electrode diameter, and the switching charge density and emission charge were measured simultaneously. The simulation of the electric field distribution showed that an asymmetric electrode structure could cause a stray field on the bare surface of the ferroelectric cathode near the edge of upper electrode. The distance of stray field from the electrode edge increased with increasing ferroelectric thickness, but it did not depend on the upper electrode diameter. The switching charge density increased more on the cathode with smaller upper electrode diameter. This was attributed to the stray field on the bare ferroelectric surface near the electrode edge, because the stray field for the asymmetric ferroelectric cathode enhanced polarization switching near the electrode edge. From the switching charge density, the distance of stray field from the electrode edge was calculated as about 11-14${\mu}{\textrm}{m}$. The threshold voltage of electron emission was 61-68 kV/cm, which was almost 3 times lager than the coercive voltage. The threshold voltage was not determined just by coercive voltage, but by strength and distance of the stray-field, which largely depended on the geometrical structure of ferroelectric cathode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1071-1079
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• 2002

This paper reports a methodology and application lot calculating distribution of the director in a liquid crystal cell by a numerical technique. To calculate distribution of the director, we applied a three dimensional finite element method (FEM) and calculated the distributions of electric potential and director in the liquid crystal cell. We have considered the free-energy density in the bulk of liquid crystal cell and calculated the switching property by the Ericksen-Leslie equation and the Laplace equation. We have calculated the optical transmission with distribution of the director by Berreman's method and confirmed the threshold voltage and the response time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.128-131
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• 2003

The number of grain is determined based on Poisson distribution in respectively different active channel and it is converted to grain size which affects to the mobility and threshold voltage. the acquired data is applied to the SPICE for observing the variation of I-V characteristic with several channel lengths. we can confirm the effect on device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.479-485
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• 2006

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin undoped Si channel for SCEs control, ale being validated for sub-20nm scaling. A novel analytical transport model for the subthreshold mode of DGMOSFETs is proposed in this paper. The model enables analysis of short channel effect such as the subthreshold swing(SS), the threshold voltage roil-off$({\Delta}V_{th})$ and the drain induced barrier lowering(DIBL). The proposed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. An approximative solution of the 2D Poisson equation is used for the distribution of electric potential, and Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The new model is used to investigate the subthreshold characteristics of a double gate MOSFET having the gate length in the nanometer range $(5-20{\sim}nm)$ with ultra thin gate oxide and channel thickness. The model is verified by comparing the subthreshold swing and the threshold voltage roll-off with 2D numerical simulations. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1260-1265
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• 2012

This paper have presented the change for subthreshold characteristics for double gate(DG) MOSFET based on scaling theory and the shape of Gaussian function. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution and consequently potential distributions have been analyzed closely for experimental results, and the subthreshold characteristics have been analyzed for the shape parameters of Gaussian function such as projected range and standard projected deviation. Since this potential model has been verified in the previous papers, we have used this model to analyze the subthreshold chatacteristics. The scaling theory is to sustain constant outputs for the change of device parameters. As a result to apply the scaling theory for DGMOSFET, we know the subthreshold characteristics have been greatly changed, and the change of threshold voltage is bigger relatively.

• Korean Journal of Optics and Photonics
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• v.12 no.2
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• pp.71-76
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• 2001

We studied quantum cryptography based on the quantum nature of light. We must reduce the intensity of the light pulse to the single photon regime for quantum cryptographic communication. Considering the noise and the quantum efficiency of the detector, however, we have to fmd a criterion for which we are able to distinguish the error caused by eavesdropping from other system noises. By changing the bias voltage of the detector and the threshold of the signal voltage, we find the safe region for which we can distribute the quantum key with positive proof of no-eavesdropping. The quantum key we used is a four state quantum key (BB84). BB84).

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.61-67
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• 2006

We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.