Browse > Article

Fabrication and Electrical Properties of Local Damascene FinFET Cell Array in Sub-60nm Feature Sized DRAM  

Kim, Yong-Sung (Korea Research Institue of Standard and Science)
Shin, Soo-Ho (Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd.)
Han, Sung-Hee (Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd.)
Yang, Seung-Chul (Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd.)
Sung, Joon-Ho (Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd.)
Lee, Dong-Jun (Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd.)
Lee, Jin-Woo (Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd.)
Chung, Tae-Young (Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd.)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.6, no.2, 2006 , pp. 61-67 More about this Journal
Abstract
We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.
Keywords
FinFET; local damascene; cell transistor; threshold voltage; channel doping; passing gate effect; p+ poly-silicon; low power DRAMs;
Citations & Related Records
연도 인용수 순위
  • Reference
1 C.H. Lee, J.M. Yoon, C. Lee, H.M. Yang, K.N. Kim, T.Y. Kim, H.S. Kang, Y.J. Ahn, D.G. Park, and Kinam Kim, 'Novel Body Tied FinFET Cell Array Transistor DRAM with Negative Word Line Operation for sub 60nm Technology and beyond,' VLSI Technical Digest, pp.l30-131, 2004   DOI
2 C. Lee, J.M. Yoon, C.H. Lee, J.C. Park, T.Y. Kim, H.S. Kang, S.K. Sung, E.S. Cho, H.J Cho, Y.J. Ahn, D.G. Park, Kinam Kim, and B.I. Ryu, 'Enhanced Data Retention of Damascene-finFET DRAM with Local Channel Implantation and <100> Fin Surface Orientation Engineering,' IEDM, pp.61-64, 2004   DOI
3 R. Katsumata, N. Tsuda, J. Idebuchi, M. Kondo, N. Aoki, S. Ito, K. Yahashi, T. Satonaka, M. Morikado, M. Kito, M. Kido, T. Tanaka, H. Aochi and T. Hamamoto, 'Fin-Array-FET on bulk silicon for sub-100nm Trench Capacitor DRAM,' VLSI Technical Digest, pp.61-62, 2003
4 J.Y. Kim, H.J. Oh, D.S. Woo, Y.S. Lee, H.H. Kim, S.E. Kim, G.W. Ha, H.J. Kim, N.J. Kang, J.M. Park, Y.S. Hwang, D.I. Kim, B.J. Park, M. Huh, B.H. Lee, S.B. Kim, M.H. Cho, M.Y. Jung, Y.I. Kim, C. Jin, D.W. Shim, M.S. Shim, C.S. Lee, W.S. Lee, J.C. Park, G.Y Jin, Y.J. Park, and Kinam Kim, 'S-RCAT(Sphere-shaped- Recess-Channel-Array Transistor) Technology for 70nm DRAM feature size and beyond,' VLSI Technical Digest, pp.34-35, 2005   DOI
5 J.Y. Kim, C.S. Lee, S.E. Kim, I.B. Chung, Y.M. Choi, B.J. Park, J.W. Lee, D.I. Kim, Y.S. Hwang, J.M. Park, D.H. Kim, N.J. Kang, M.H. Cho, M.Y. Jeong, H.J. Kim, J.N. Han, S.Y. Kim, B.Y. Nam, H.S. Park, S.H. Chung, J.H. Lee, J.S. Park, H.S. Kim, Y.J. Park and Kinam Kim, 'The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88nm feature size and beyond,' VLSI Technical Digest, pp.11-12, 2003
6 Y.S. Kim, S.H. Lee, S.H. Shin, S.H. Han, J.Y. Lee, J.W. Lee, J. Han, S.C. Yang, J.H. Sung, E.C. Lee, B.Y. Song, DJ. Lee, D.I. Bae, W.S. Yang, Y.K. Park, K.H. Lee, B.H. Roh, T.Y. Chung, Kinam Kim, and Wonshik Lee, 'Local-Damascene-FinFET DRAM Integration with p+ Doped Poly-Silicon Gate Technology for sub-60nm Device Generations,' IEDM, pp.325-328, 2005